Xilinx EDK 8.2i manual Ffff, Cicacheusefsl, Cdcacheusefsl

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Chapter 2: MicroBlaze Signal Interface Description

Table 2-12:MPD Parameters

Parameter Name	Feature/Description	Allowable	Default	EDK Tool	VHDL
		Values	Value	Assigned	Type
C_ICACHE_HIGHADDR	Instruction cache high	0x00000000 -	0x3FFF		std_logi
	address	0xFFFFFFFF	FFFF		c_vector
C_USE_ICACHE	Instruction cache	0, 1	0		integer
C_ALLOW_ICACHE_WR	Instruction cache write	0, 1	1		integer
	enable
C_ICACHE_LINELEN	Instruction cache line	4, 8	4		integer
	length
C_ADDR_TAG_BITS	Instruction cache address	0-21	17	yes	integer
	tags
C_CACHE_BYTE_SIZE	Instruction cache size	2048, 4096,	8192		integer
		8192, 16384,
		32768,
		655361
C_ICACHE_USE_FSL	Cache over CacheLink	1	1		integer
	instead of OPB for
	instructions
C_DCACHE_BASEADDR	Data cache base address	0x00000000 -	0x0000		std_logi
		0xFFFFFFFF	0000		c_vector
C_DCACHE_HIGHADDR	Data cache high address	0x00000000 -	0x3FFF		std_logi
		0xFFFFFFFF	FFFF		c_vector
C_USE_DCACHE	Data cache	0,1	0		integer
C_ALLOW_DCACHE_WR	Data cache write enable	0,1	1		integer
C_DCACHE_LINELEN	Data cache line length	4, 8	4		integer
C_DCACHE_ADDR_TAG	Data cache address tags	0-20	17	yes	integer
C_DCACHE_BYTE_SIZE	Data cache size	2048, 4096,	8192		integer
		8192, 16384,
		32768,
		655362
C_DCACHE_USE_FSL	Cache over CacheLink	1	1		integer
	instead of OPB for data

1.Not all sizes are permitted in all architectures. The cache will use between 1 and 32 RAMB primitives.

2.Not all sizes are permitted in all architectures. The cache will use between 1 and 32 RAMB primitives.

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	1-800-255-7778	UG081 (v6.0) June 1, 2006