Local Memory Bus LMB Interface Description | Xilinx EDK 8.2i

Local Memory Bus (LMB) Interface Description

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Local Memory Bus (LMB) Interface Description

The LMB is a synchronous bus used primarily to access on-chip block RAM. It uses a minimum number of control signals and a simple protocol to ensure that local block RAM are accessed in a single clock cycle. LMB signals and deﬁnitions are shown in the following table. All LMB signals are active high.

LMB Signal Interface

Table 2-2:LMB Bus Signals

	Signal	Data Interface	Instruction	Type	Description
	Signal	Data Interface	Interface	Type	Description
			Interface

	Addr[0:31]	Data_Addr[0:31]	Instr_Addr[0:31]	O	Address bus

	Byte_Enable[0:3]	Byte_Enable[0:3]	not used	O	Byte enables

	Data_Write[0:31]	Data_Write[0:31]	not used	O	Write data bus

	AS	D_AS	I_AS	O	Address strobe

	Read_Strobe	Read_Strobe	IFetch	O	Read in progress

	Write_Strobe	Write_Strobe	not used	O	Write in progress

	Data_Read[0:31]	Data_Read[0:31]	Instr[0:31]	I	Read data bus

	Ready	DReady	IReady	I	Ready for next transfer

	Clk	Clk	Clk	I	Bus clock

Addr[0:31]

The address bus is an output from the core and indicates the memory address that is being accessed by the current transfer. It is valid only when AS is high. In multicycle accesses (accesses requiring more than one clock cycle to complete), Addr[0:31] is valid only in the ﬁrst clock cycle of the transfer.

Byte_Enable[0:3]

The byte enable signals are outputs from the core and indicate which byte lanes of the data bus contain valid data. Byte_Enable[0:3] is valid only when AS is high. In multicycle accesses (accesses requiring more than one clock cycle to complete), Byte_Enable[0:3] is valid only in the ﬁrst clock cycle of the transfer. Valid values for Byte_Enable[0:3] are shown in the following table:

Table 2-3:Valid Values for Byte_Enable[0:3]

		Byte Lanes Used

Byte_Enable[0:3]	Data[0:7]	Data[8:15]	Data[16:23]	Data[24:31]

0000

0001				x

0010			x

0100		x

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UG081 (v6.0) June 1, 2006	1-800-255-7778

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Xilinx EDK 8.2i manual Local Memory Bus LMB Interface Description, LMB Signal Interface, Addr031, ByteEnable03

Contents

UG081 v6.0 June 1 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide Date Version Revision MicroBlaze Processor Reference Guide UG081 v6.0 June 1 UG081 v6.0 June 1 Preface About This Guide MicroBlaze Application Binary Interface Additional Resources Manual Contents Typographical Conventions Conventions Meaning or Use Example Online Document UG081 v6.0 June 1 Overview Features Version Status Deprecated Active MicroBlaze Architecture Instructions Data Types and Endianness ESR MSREAR FSR Op1 if cond else op2 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 Registers Special Purpose Registers General Purpose RegistersProgram Counter PC Registers Machine Status Register MSR 8Program Counter PC Bits Name Description Reset Value9Machine Status Register MSR Bits Name Description PVR DCE EIPICE FSL Exception Address Register EAR Buslock Enable ESS Exception Status Register ESR Source/Destination Register Branch Target Register BTR Processor Version Register PVR Floating Point Status Register FSR Cusebarrel CFGDIV Cusediv OP0EXEC CdebugenabledUnexec Cunalignedexception Cicachelinelen IcllIcbs Ccachebytesize Pipeline Architecture CresetmsrArch Rstmsr Memory Architecture Delay SlotsBranches Reset, Interrupts, Exceptions, and Break Reset, Interrupts, Exceptions, and Break Hardware Exceptions ResetEquivalent Pseudocode Exception Causes Hardware Breaks Breaks User Vector Exception InterruptSoftware Breaks Latency Overview Instruction CacheGeneral Instruction Cache Functionality Instruction Cache Instruction Cache Operation Data CacheInstruction Cache Software Support MSR Bit Data Cache Operation General Data Cache FunctionalityData Cache Data Cache Software Support Floating Point Unit FPUWDC Instruction Rounding FormatOperations Arithmetic Fast Simplex Link FSL Hardware Acceleration using FSLExceptions Comparison Debug Overview Debug and TraceTrace Overview MicroBlaze Architecture Ilmb MicroBlaze I/O OverviewIxcl Dxcl Dmrnw Dopb MicroBlaze Signal Interface Description DAS Dlmb Imrnw IopbIAS Ilmb Mfsl Ixclm On-Chip Peripheral Bus OPB Interface DescriptionDxcls Dxclm ByteEnable03 LMB Signal InterfaceLocal Memory Bus LMB Interface Description Addr031 ReadStrobe DataWrite031WriteStrobe DataRead031 Generic Write Operation LMB TransactionsGeneric Read Operation Single Cycle Back-to-Back Read Operation Back-to-Back Write OperationBack-to-Back Mixed Read/Write Operation BE0 BE1 BE2 RD1623 RD2431 Read and Write Data SteeringRD07 RD815 RD1623 RD2431 Slave FSL Signal Interface Master FSL Signal InterfaceFast Simplex Link FSL Interface Description FSL Transactions Xilinx CacheLink XCL Interface DescriptionFSL BUS Write Operation FSL BUS Read Operation CacheLink Signal Interface CacheLink Transactions Data Cache Read Miss Instruction Cache Read MissData Cache Write Trace Interface Description Debug Interface DescriptionDebug Interface Description MDM MicroBlaze Processor Reference Guide 11 Type of Trace Exception TraceExceptionKind Description MicroBlaze Core Conﬁgurability Values Assigned Type Cusemsrinstr CusepcmpinstrPcmpne Cunalignedexception Cnumberofrdaddrbrk Cicacheusefsl FfffCdcacheusefsl Data Types Scope MicroBlaze Application Binary Interface Register Usage Conventions2Register usage conventions Type Enforcement Purpose Stack Convention Stack Convention High Memory Low Memory Func Memory Model Interrupt and Exception Handling Summary 1Symbol notation MeaningNotation Type a FormatsType B Opcode Destination Reg Source Reg a Immediate Value Description AddRegisters Altered Addi RD, rA, rB Registers Altered Latency Logial and with Immediate Andi RD, rA, IMM Andi Logical and not AndnAndn RD, rA, rB Logical and not with Immediate Andni RD, rA, IMM Andni Branch if Equal Beq BeqBeqd Branch Immediate if Equal Beqi BeqiBeqid Branch if Greater or Equal Bge BgeBged Branch Immediate if Greater or Equal Bgei BgeiBgeid Branch if Greater Than Bgt BgtBgtd Branch Immediate if Greater Than Bgti BgtiBgtid Branch if Less or Equal Ble BleBled Branch Immediate if Less or Equal Blei BleiBleid Branch if Less Than Blt Blt Blti BltiBltid Branch if Not Equal Bne BneBned Branch Immediate if Not Equal Bnei BneiBneid Bra Instructions Unconditional BranchBrd Brad MicroBlaze Instruction Set Architecture Bri MicroBlaze Instruction Set Architecture Msrbip Instructions BrkBreak RD, rB Break Immediate Brki RD, IMM Brki Bsra Instructions Barrel Shift BsrlBsll Barrel Shift Immediate Bsrli BsiBsrai Bslli Integer Compare Cmp CmpCmpu Floating Point Arithmetic Add Fadd FaddEsrec FSRIO,UF,OF,DO Reverse Floating Point Arithmetic Subtraction FrsubFrsub RD, rA, rB Reverse subtract Floating Point Arithmetic Multiplication Fmul Fmul Floating Point Arithmetic Division FdivFdiv RD, rA, rB Divide Esrec FSRIO,UF,OF,DO,DZ Fcmp Esrec FSRIO,DO Get from fsl interface GetNget Cget Integer Divide Idiv IdivIdivu Immediate ImmIMM Imm Load Byte Unsigned LbuLbu RD, rA, rB Load Byte Unsigned Immediate Lbui RD, rA, IMM Lbui Lhu RD, rA, rB Lhu Load Halfword Unsigned Immediate Lhui RD, rA, IMM Lhui Load Word Load Word Immediate Lwi RD, rA, IMM Lwi Mfs RD, rS Mfs Read MSR and clear bits in MSR Msrclr RD, Imm Msrclr Msrset RD, Imm Msrset Move To Special Purpose Register Mts RS, rA Mts Instructions Mul Multiply RD, rA, rB Multiply Immediate Muli RD, rA, IMM Muli Logical or Logical or with Immediate Ori RD, rA, IMM Ori Pattern Compare Byte Find Pcmpbf Pcmpbf Pattern Compare Equal Pcmpeq Pcmpeq Pattern Compare Not Equal Pcmpne Pcmpne Put to fsl interface PutNput Cput Arithmetic Reverse Subtract Rsub RsubRsubc Rsubk Arithmetic Reverse Subtract Immediate Rsubi RsubiRsubic Rsubik Return from Break RtbdRtbd RA, IMM Return from Interrupt Rtid RA, IMM RtidMsrie Return from Exception Rted RA, IMM RtedMsree Msreip ESR Return from Subroutine Rtsd RA, IMM Rtsd None Store Byte Immediate Sbi RD, rA, IMM Sbi Sext16 RD, rA Sext16 Sign Extend Byte Sext8Sext8 RD, rA Instructions Store Halfword RD, rA, rB Store Halfword Immediate Shi RD, rA, IMM Shi Sra RD, rA Sra Shift Right with Carry Src RD, rA Src Shift Right Logical SrlSrl RD, rA Addr ← rA + rB Addr3031 ← MemAddr ← rD031 Store Word Immediate Swi RD, rA, IMM Register Altered Write to Data Cache Wdc Wic Logical Exclusive or Xor RD, rA, rB Xor Logical Exclusive or with Immediate XoriXori RA, rD, IMM 148