Xilinx EDK 8.2i manual Reset, Hardware Exceptions, Equivalent Pseudocode, Exception Causes

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Chapter 1: MicroBlaze Architecture

Reset

When a Reset or Debug_Rst(1) occurs, MicroBlaze will flush the pipeline and start fetching instructions from the reset vector (address 0x0). Both external reset signals are active high, and should be asserted for a minimum of 16 cycles.

Equivalent Pseudocode

PC ← 0x00000000

MSR ← C_RESET_MSR (see “MicroBlaze Core Configurability” in Chapter 2)

EAR ← 0

ESR ← 0

FSR ← 0

Hardware Exceptions

MicroBlaze can be configured to trap the following internal error conditions: illegal instruction, instruction and data bus error, and unaligned access. The divide by zero exception can only be enabled if the processor is configured with a hardware divider (C_USE_DIV=1). When configured with a hardware floating point unit (C_USE_FPU=1), it can also trap the following floating point specific exceptions: underflow, overflow, float division-by-zero, invalid operation, and denormalized operand error.

A hardware exception will cause MicroBlaze to flush the pipeline and branch to the hardware exception vector (address 0x20). The exception will also load the decode stage program counter value into the general purpose register R17. The execution stage instruction in the exception cycle is not executed. If the exception is caused by an instruction in a branch delay slot, then the ESR[DS] bit will be set. In this case the exception handler should resume execution from the branch target address, stored in BTR.

The EE and EIP bits in MSR are automatically reverted when executing the RTED instruction.

Exception Causes

•Instruction Bus Exception

The instruction On-chip Peripheral Bus exception is caused by an active error signal from the slave (IOPB_errAck) or timeout signal from the arbiter (IOPB_timeout). The instructions side local memory (ILMB) and CacheLink (IXCL) interfaces can not cause instruction bus exceptions.

•Illegal Opcode Exception

The illegal opcode exception is caused by an instruction with an invalid major opcode (bits 0 through 5 of instruction). Bits 6 through 31 of the instruction are not checked. Optional processor instructions are detected as illegal if not enabled.

•Data Bus Exception

The data On-chip Peripheral Bus exception is caused by an active error signal from the slave (DOPB_errAck) or timeout signal from the arbiter (DOPB_timeout). The data side local memory (DLMB) and CacheLink (DXCL) interfaces can not cause data bus exceptions.

1.Reset input controlled by the XMD debugger via MDM

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