Branch Target Register BTR | Xilinx EDK 8.2i instruction

R

Chapter 1: MicroBlaze Architecture

Table 1-12:Exception Speciﬁc Status (ESS)

	Exception	Bits	Name	Description	Reset Value
	Cause	Bits	Name	Description	Reset Value
	Cause

	Unaligned	20	W	Word Access Exception	0
	Data Access			0 unaligned halfword access
				0 unaligned halfword access
				1 unaligned word access

		21	S	Store Access Exception	0
				0 unaligned load access
				1 unaligned store access

		22:26	Rx	Source/Destination Register	0
				General purpose register used
				as source (Store) or destination
				(Load) in unaligned access

	Illegal	20:26	Reserved		0
	Instruction

	Instruction	20:26	Reserved		0
	bus error

	Data bus	20:26	Reserved		0
	error

	Divide by	20:26	Reserved		0
	zero

	Floating	20:26	Reserved		0
	point unit

Branch Target Register (BTR)

The Branch Target Register only exists if the MicroBlaze processor is conﬁgured to use exceptions. The register stores the branch target address for all delay slot branch instructions executed while MSR[EIP] = 0. If an exception is caused by an instruction in a delay slot (i.e. ESR[DS]=1) then the exception handler should return execution to the address stored in BTR instead of the normal exception return address stored in r17. When read with the MFS instruction the BTR is speciﬁed by setting Sa = 0x000B.

0

31

↑

BTR

Figure 1-7: BTR

26	www.xilinx.com	MicroBlaze Processor Reference Guide
	1-800-255-7778	UG081 (v6.0) June 1, 2006

Image 26

Xilinx EDK 8.2i manual Branch Target Register BTR, Source/Destination Register

Contents

MicroBlaze Processor Reference Guide UG081 v6.0 June 1 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 Date Version Revision UG081 v6.0 June 1 Preface About This Guide MicroBlaze Application Binary Interface Manual Contents Additional Resources Conventions Typographical Online Document Conventions Meaning or Use Example UG081 v6.0 June 1 Features Overview MicroBlaze Architecture Version Status Deprecated Active Data Types and Endianness Instructions EAR MSRESR FSR Op1 if cond else op2 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 MicroBlaze Processor Reference Guide MicroBlaze Processor Reference Guide UG081 v6.0 June 1 Registers Program Counter PC General Purpose RegistersSpecial Purpose Registers Registers 9Machine Status Register MSR Bits Name Description 8Program Counter PC Bits Name Description Reset ValueMachine Status Register MSR PVR ICE EIPDCE FSL Buslock Enable Exception Address Register EAR Exception Status Register ESR ESS Branch Target Register BTR Source/Destination Register Floating Point Status Register FSR Processor Version Register PVR DIV CFGCusebarrel Cusediv Unexec CdebugenabledOP0EXEC Cunalignedexception Icbs IcllCicachelinelen Ccachebytesize Arch CresetmsrPipeline Architecture Rstmsr Branches Delay SlotsMemory Architecture Reset, Interrupts, Exceptions, and Break Reset, Interrupts, Exceptions, and Break Equivalent Pseudocode ResetHardware Exceptions Exception Causes Breaks Hardware Breaks Software Breaks InterruptUser Vector Exception Latency General Instruction Cache Functionality Instruction CacheOverview Instruction Cache Instruction Cache Software Support Data CacheInstruction Cache Operation MSR Bit Data Cache General Data Cache FunctionalityData Cache Operation WDC Instruction Floating Point Unit FPUData Cache Software Support Operations FormatRounding Arithmetic Exceptions Hardware Acceleration using FSLFast Simplex Link FSL Comparison Trace Overview Debug and TraceDebug Overview MicroBlaze Architecture Ixcl MicroBlaze I/O OverviewIlmb Dxcl MicroBlaze Signal Interface Description Dmrnw Dopb IAS Ilmb Imrnw IopbDAS Dlmb Mfsl Dxcls On-Chip Peripheral Bus OPB Interface DescriptionIxclm Dxclm Local Memory Bus LMB Interface Description LMB Signal InterfaceByteEnable03 Addr031 WriteStrobe DataWrite031ReadStrobe DataRead031 Generic Read Operation LMB TransactionsGeneric Write Operation Back-to-Back Mixed Read/Write Operation Back-to-Back Write OperationSingle Cycle Back-to-Back Read Operation BE0 BE1 BE2 RD07 RD815 RD1623 RD2431 Read and Write Data SteeringRD1623 RD2431 Fast Simplex Link FSL Interface Description Master FSL Signal InterfaceSlave FSL Signal Interface FSL BUS Write Operation Xilinx CacheLink XCL Interface DescriptionFSL Transactions FSL BUS Read Operation CacheLink Signal Interface CacheLink Transactions Data Cache Write Instruction Cache Read MissData Cache Read Miss Debug Interface Description Debug Interface DescriptionTrace Interface Description MDM MicroBlaze Processor Reference Guide MicroBlaze Core Conﬁgurability 11 Type of Trace Exception TraceExceptionKind Description Values Assigned Type Pcmpne Cunalignedexception CusepcmpinstrCusemsrinstr Cnumberofrdaddrbrk Cdcacheusefsl FfffCicacheusefsl Scope Data Types 2Register usage conventions Type Enforcement Purpose Register Usage ConventionsMicroBlaze Application Binary Interface Stack Convention Stack Convention High Memory Low Memory Func Memory Model Interrupt and Exception Handling Notation 1Symbol notation MeaningSummary Type B FormatsType a Opcode Destination Reg Source Reg a Immediate Value Registers Altered AddDescription Addi Registers Altered Latency RD, rA, rB Andi Logial and with Immediate Andi RD, rA, IMM Andn RD, rA, rB AndnLogical and not Andni Logical and not with Immediate Andni RD, rA, IMM Beqd BeqBranch if Equal Beq Beqid BeqiBranch Immediate if Equal Beqi Bged BgeBranch if Greater or Equal Bge Bgeid BgeiBranch Immediate if Greater or Equal Bgei Bgtd BgtBranch if Greater Than Bgt Bgtid BgtiBranch Immediate if Greater Than Bgti Bled BleBranch if Less or Equal Ble Bleid BleiBranch Immediate if Less or Equal Blei Blt Branch if Less Than Blt Bltid BltiBlti Bned BneBranch if Not Equal Bne Bneid BneiBranch Immediate if Not Equal Bnei Brd Instructions Unconditional BranchBra Brad MicroBlaze Instruction Set Architecture Bri MicroBlaze Instruction Set Architecture Instructions BrkBreak RD, rB Msrbip Brki Break Immediate Brki RD, IMM Bsll Instructions Barrel Shift BsrlBsra Bsrai BsiBarrel Shift Immediate Bsrli Bslli Cmpu CmpInteger Compare Cmp Esrec FSRIO,UF,OF,DO FaddFloating Point Arithmetic Add Fadd Frsub RD, rA, rB Reverse subtract FrsubReverse Floating Point Arithmetic Subtraction Fmul Floating Point Arithmetic Multiplication Fmul Fdiv RD, rA, rB Divide FdivFloating Point Arithmetic Division Esrec FSRIO,UF,OF,DO,DZ Fcmp Esrec FSRIO,DO Nget GetGet from fsl interface Cget Idivu IdivInteger Divide Idiv Imm Immediate ImmIMM Lbu RD, rA, rB LbuLoad Byte Unsigned Lbui Load Byte Unsigned Immediate Lbui RD, rA, IMM Lhu Lhu RD, rA, rB Lhui Load Halfword Unsigned Immediate Lhui RD, rA, IMM Load Word Lwi Load Word Immediate Lwi RD, rA, IMM Mfs Mfs RD, rS Msrclr Read MSR and clear bits in MSR Msrclr RD, Imm Msrset Msrset RD, Imm Mts Move To Special Purpose Register Mts RS, rA Instructions Mul Multiply RD, rA, rB Muli Multiply Immediate Muli RD, rA, IMM Logical or Ori Logical or with Immediate Ori RD, rA, IMM Pcmpbf Pattern Compare Byte Find Pcmpbf Pcmpeq Pattern Compare Equal Pcmpeq Pcmpne Pattern Compare Not Equal Pcmpne Nput PutPut to fsl interface Cput Rsubc RsubArithmetic Reverse Subtract Rsub Rsubk Rsubic RsubiArithmetic Reverse Subtract Immediate Rsubi Rsubik Rtbd RA, IMM RtbdReturn from Break Msrie RtidReturn from Interrupt Rtid RA, IMM Msree Msreip ESR RtedReturn from Exception Rted RA, IMM Rtsd Return from Subroutine Rtsd RA, IMM None Sbi Store Byte Immediate Sbi RD, rA, IMM Sext16 Sext16 RD, rA Sext8 RD, rA Sext8Sign Extend Byte Instructions Store Halfword RD, rA, rB Shi Store Halfword Immediate Shi RD, rA, IMM Sra Sra RD, rA Src Shift Right with Carry Src RD, rA Srl RD, rA SrlShift Right Logical Addr ← rA + rB Addr3031 ← MemAddr ← rD031 Register Altered Store Word Immediate Swi RD, rA, IMM Wdc Write to Data Cache Wic Xor Logical Exclusive or Xor RD, rA, rB Xori RA, rD, IMM XoriLogical Exclusive or with Immediate 148