Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Datasheet

Table 8.1 Read After Write Timing Rules

 

MINIMUM WAIT TIME FOR

NUMBER OF BYTE_TEST

 

READ FOLLOWING ANY

READS

REGISTER NAME

WRITE CYCLE (IN NS)

(ASSUMING TCYC OF 45NS)

RX Data FIFO

0

0

 

 

 

RX Status FIFO

0

0

 

 

 

RX Status FIFO PEEK

0

0

 

 

 

TX Status FIFO

0

0

 

 

 

TX Status FIFO PEEK

0

0

 

 

 

ID_REV

0

0

 

 

 

IRQ_CFG

135

3

 

 

 

INT_STS

90

2

 

 

 

INT_EN

45

1

 

 

 

BYTE_TEST

0

0

 

 

 

FIFO_INT

45

1

 

 

 

RX_CFG

45

1

 

 

 

TX_CFG

45

1

 

 

 

HW_CFG

45

1

 

 

 

RX_DP_CTRL

45

1

 

 

 

RX_FIFO_INF

0

0

 

 

 

TX_FIFO_INF

135

3

 

 

 

PMT_CTRL

315

7

 

 

 

GPT_CFG

45

1

 

 

 

GPT_CNT

135

3

 

 

 

FREE_RUN

180

4

 

 

 

RX_DROP

0

0

 

 

 

MAC_CSR_CMD

45

1

 

 

 

MAC_CSR_DATA

45

1

 

 

 

AFC_CFG

45

1

 

 

 

1588_CLOCK_HI_RX_CAPTURE_1

0

0

 

 

 

1588_CLOCK_LO_RX_CAPTURE_1

0

0

 

 

 

1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_1

0

0

 

 

 

1588_SRC_UUID_LO_RX_CAPTURE_1

0

0

 

 

 

1588_CLOCK_HI_TX_CAPTURE_1

0

0

 

 

 

1588_CLOCK_LO_TX_CAPTURE_1

0

0

 

 

 

SMSC LAN9311/LAN9311i

103

Revision 1.4 (08-19-08)

 

DATASHEET