Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Datasheet

Figure 10.2 displays the various bus states of a typical I2C cycle.

data

data

data

data

data

data

can

can

can

can

change

stable

change

change

stable

change

EE_SDA

 

 

 

 

 

S

 

Sr

 

 

P

EE_SCL

 

 

 

 

 

Start Condition

Data Valid

Re-Start

 

Data Valid

Stop Condition

or Ack

Condition

 

or Ack

 

 

 

 

Figure 10.2 I2C Cycle

10.2.2.2I2C EEPROM Device Addressing

The I2C EEPROM is addressed for a read or write operation by first sending a control byte followed by the address byte or bytes. The control byte is preceded by a start condition. The control byte and address byte(s) are each acknowledged by the EEPROM slave. If the EEPROM slave fails to send an acknowledge, then the sequence is aborted and the EPC_TIMEOUT bit of the EEPROM Command Register (E2P_CMD) is set.

The control byte consists of a 4-bit control code, 3-bits of chip/block select and one direction bit. The control code is 1010b. For single byte addressing EEPROMs, the chip/block select bits are used for address bits 10, 9, and 8. For double byte addressing EEPROMs, the chip/block select bits are set low. The direction bit is set low to indicate the address is being written.

Figure 10.3 illustrates typical I2C EEPROM addressing bit order for single and double byte addressing.

Control Byte

S

1

0

1

0

A

A

A

0

01

9

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Address Byte

A A A A A A A A A A CK 7 6 5 4 3 2 1 0 CK

 

 

 

Control Byte

 

 

 

 

 

 

Address High

 

 

 

Address Low

 

 

 

 

 

 

 

A

 

 

 

 

Byte

 

 

 

 

A

 

 

 

 

Byte

 

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S

1

0

1

0

0

0

0

0

A

A

A

A

A

A

A

A

A

 

A

A

A

A

A

A

A

C

1

 

1

1

1

1

1

9

8

C

7

6

5

4

3

2

1

 

0

C

 

 

 

 

 

 

 

 

 

 

 

 

 

K

5

 

4

3

2

1

0

K

 

K

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Chip / Block R/~W

Chip / Block R/~W

Select Bits

Select Bits

Single Byte Addressing

Double Byte Addressing

 

Figure 10.3 I2C EEPROM Addressing

Revision 1.4 (08-19-08)

142

SMSC LAN9311/LAN9311i

 

DATASHEET