Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Datasheet

14.2.9.7Free Running 25MHz Counter Register (FREE_RUN)

Offset:

09Ch

Size:

32 bits

This read-only register reflects the current value of the free-running 25MHz counter. Refer to Section 12.2, "Free-Running Clock," on page 162 for additional information.

BITS

 

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

31:0

Free Running Counter (FR_CNT)

RO

00000000h

 

This field reflects the current value of the free-running 32-bit counter. At

 

 

 

reset, the counter starts at zero and is incremented by one every 25MHz

 

 

 

cycle. When the maximum count has been reached, the counter will rollover

 

 

 

to zero and continue counting.

 

 

 

Note:

The count value is latched on the first read. This eliminates

 

 

 

 

erroneous readings of the full free running counter value.

 

 

 

Note:

The free running counter can take up to 160nS to clear after a reset

 

 

 

 

event.

 

 

 

 

 

 

 

SMSC LAN9311/LAN9311i

269

Revision 1.4 (08-19-08)

 

DATASHEET