Two Port 10/100 Managed Ethernet Switch with
Datasheet
14.3.6Host MAC MII Access Register (HMAC_MII_ACC)
Offset: | 6h | Size: | 32 bits |
This read/write register is used in conjunction with the Host MAC MII Data Register (HMAC_MII_DATA) to access the internal PHY registers. Refer to Section 14.4, "Ethernet PHY Control and Status Registers" for a list of accessible PHY registers and PHY address information.
BITS | DESCRIPTION | TYPE | DEFAULT |
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31:16 | RESERVED | RO | - |
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15:11 | PHY Address (PHY_ADDR) | R/W | 00000b |
| This field must be loaded with the PHY address that the MII access is |
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| intended for. A list default PHY addresses can be seen in Table 7.1. Refer |
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| to Section 7.1.1, "PHY Addressing," on page 82 for additional information on |
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| PHY addressing. |
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10:6 | MII Register Index (MIIRINDA) | R/W | 00000b |
| These bits select the desired MII register in the PHY. |
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5:2 | RESERVED | RO | - |
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1 | MII Write (MIIWnR) | R/W | 0b |
| Setting this bit tells the PHY that this will be a write operation using the Host |
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| MAC MII Data Register (HMAC_MII_DATA). If this bit is cleared, a read |
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| operation will occur, packing the data in the Host MAC MII Data Register |
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0 | MII Busy (MIIBZY) | R/W | 0b |
| This bit must be polled to determine when the MII register access is | SC |
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| complete. This bit must read a logical 0 before writing to this register or the |
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| The LAN driver software must set this bit in order for the |
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| LAN9311/LAN9311i to read or write any of the MII PHY registers. |
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| During a MII register access, this bit will be set, signifying a read or write |
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| access is in progress. The MII data register must be kept valid until the Host |
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| MAC clears this bit during a PHY write operation. The MII data register is |
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| invalid until the Host MAC has cleared this bit during a PHY read operation. |
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SMSC LAN9311/LAN9311i | 279 | Revision 1.4 |
| DATASHEET |
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