Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Datasheet

8.5.6RX Data FIFO Direct PIO Reads

In this mode only A[2:1] are decoded, and any read of the LAN9311/LAN9311i will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its address when accessing the LAN9311/LAN9311i.

Timing is identical to a PIO read and the FIFO_SEL and END_SEL signals have the same timing characteristics as the address lines. An RX Data FIFO direct PIO read cycle begins when both nCS and nRD are asserted. Either or both of these control signals must de-assert between cycles for the period specified in Table 15.10, “RX Data FIFO Direct PIO Read Cycle Timing Values,” on page 450. The cycle ends when either or both nCS and nRD are de-asserted. These signals may be asserted and de-asserted in any order. Read data is valid as indicated in the functional timing diagram in Figure 8.5.

Note: Address lines A[2:1] are still used, and address lines A[9:3] are ignored.

Please refer to Section 15.5.6, "RX Data FIFO Direct PIO Read Cycle Timing," on page 450 for the AC timing specifications for RX Data FIFO direct PIO read operations.

FIFO_SEL

 

 

 

 

 

 

 

 

END_SEL

 

 

 

 

 

 

 

 

 

 

 

VALID

 

 

A[x:3]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A[2:1]

 

 

 

 

 

 

 

VALID

 

nCS, nRD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D[15:0] (OUTPUT)

 

 

 

 

 

 

 

 

 

 

 

 

VALID

 

 

 

 

 

 

 

 

 

(READ DATA FROM RX DATA FIFO)

Figure 8.5 Functional Timing for RX Data FIFO Direct PIO Read Operation

SMSC LAN9311/LAN9311i

109

Revision 1.4 (08-19-08)

 

DATASHEET