Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Datasheet

14.2.8.4Virtual PHY Identification LSB Register (VPHY_ID_LSB)

Offset:

1CCh

Size:

32 bits

Index (decimal):

3

 

 

This read/write register contains the LSB of the Virtual PHY Organizationally Unique Identifier (OUI). The MSB of the Virtual PHY OUI is contained in the Virtual PHY Identification MSB Register (VPHY_ID_MSB).

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

31:16

RESERVED

RO

-

 

(See Note 14.25)

 

 

 

 

 

 

15:10

PHY ID

R/W

00h

 

This field contains the lower 6-bits of the Virtual PHY OUI (Note 14.26).

 

 

 

 

 

 

9:4

Model Number

R/W

00h

 

This field contains the 6-bit manufacturer’s model number of the Virtual PHY

 

 

 

(Note 14.26).

 

 

 

 

 

 

3:0

Revision Number

R/W

0h

 

This field contain the 4-bit manufacturer’s revision number of the Virtual PHY

 

 

 

(Note 14.26).

 

 

 

 

 

 

Note 14.25 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on a DWORD boundary. When accessed serially (through the MII management protocol), the register is 16-bits wide.

Note 14.26 IEEE allows a value of zero in each of the 32-bits of the PHY Identifier.

Revision 1.4 (08-19-08)

252

SMSC LAN9311/LAN9311i

 

DATASHEET