Two Port 10/100 Managed Ethernet Switch with
Datasheet
14.2.9.8Reset Control Register (RESET_CTL)
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| Offset: | 1F8h | Size: | 32 bits |
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| This register contains software controlled resets. |
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| Note: This register can be read while the LAN9311/LAN9311i is in the reset or not ready states. | |||||||
| Note: Either half of this register can be read without the need to read the other half. |
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BITS |
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| DESCRIPTION |
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| TYPE |
| DEFAULT |
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31:4 | RESERVED |
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| RO |
| - | |
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3 | Virtual PHY Reset (VPHY_RST) |
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| R/W |
| 0b | ||
| Setting this bit resets the Virtual PHY. When the Virtual PHY is released from | SC |
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| reset, this bit is automatically cleared. All writes to this bit are ignored while |
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| this bit is set. |
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| Note: | This bit is not accessible via the EEPROM Loader. |
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2 | Port 2 PHY Reset (PHY2_RST) |
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| R/W |
| 0b | ||
| Setting this bit resets the Port 2 PHY. The internal logic automatically holds | SC |
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| the PHY reset for a minimum of 102uS. When the Port 2 PHY is released |
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| from reset, this bit is automatically cleared. All writes to this bit are ignored |
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| while this bit is set. |
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| Note: | This bit is not accessible via the EEPROM Loader. |
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1 | Port 1 PHY Reset (PHY1_RST) |
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| R/W |
| 0b | ||
| Setting this bit resets the Port 1 PHY. The internal logic automatically holds | SC |
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| the PHY reset for a minimum of 102uS. When the Port 1 PHY is released |
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| from reset, this bit is automatically cleared. All writes to this bit are ignored |
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| while this bit is set. |
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| Note: | This bit is not accessible via the EEPROM Loader. |
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0 | Digital Reset (DIGITAL_RST) |
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| R/W |
| 0b | ||
| Setting this bit resets the complete chip except the PLL, Virtual PHY, Port 1 | SC |
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| PHY, and Port 2 PHY. The EEPROM Loader will automatically reload the |
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| configuration following this reset, but will not reset the Virtual PHY, Port 1 |
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| PHY, or Port 2 PHY. If desired, the above PHY resets can be issued once |
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| the device is configured. All system CSRs are reset except for any NASR |
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| type bits. Any in progress EEPROM commands (including RELOAD) are |
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| terminated. |
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| When the chip is released from reset, this bit is automatically cleared. This |
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| bit should be polled to determine when the reset is complete. All writes to |
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| this bit are ignored while this bit is set. |
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| Note: | The LAN9311/LAN9311imust always be read at least once after |
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| Note: | This bit is not accessible via the EEPROM Loader. |
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Revision 1.4 | 270 | SMSC LAN9311/LAN9311i |
| DATASHEET |
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