Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Datasheet

14.5.3.27Switch Engine Ingress Rate Command Status Register (SWE_INGRSS_RATE_CMD_STS)

Register #:

184Ch

Size:

32 bits

This register indicates the current ingress rate command status.

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

31:1

RESERVED

RO

-

 

 

 

 

0

Operation Pending

RO

0b

 

When set, indicates that the read or write command is taking place. This bit

SC

 

 

is cleared once the command has finished.

 

 

 

 

 

 

Revision 1.4 (08-19-08)

398

SMSC LAN9311/LAN9311i

 

DATASHEET