Two Port 10/100 Managed Ethernet Switch with
Datasheet
14.2.1.2Interrupt Status Register (INT_STS)Offset: | 058h | Size: | 32 bits |
This register contains the current status of the generated interrupts. A value of 1 indicates the corresponding interrupt conditions have been met, while a value of 0 indicates the interrupt conditions have not been met. The bits of this register reflect the status of the interrupt source regardless of whether the source has been enabled as an interrupt in the Interrupt Enable Register (INT_EN). Where indicated as R/WC, writing a 1 to the corresponding bits acknowledges and clears the interrupt.
BITS | DESCRIPTION | TYPE | DEFAULT |
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31 | Software Interrupt (SW_INT) | R/WC | 0b |
| This interrupt is generated when the SW_INT_EN bit of the Interrupt Enable |
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| Register (INT_EN) is set high. Writing a one clears this interrupt. |
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30 | Device Ready (READY) | R/WC | 0b |
| This interrupt indicates that the LAN9311/LAN9311i is ready to be accessed |
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| after a |
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29 | 1588 Interrupt Event (1588_EVNT) | RO | 0b |
| This bit indicates an interrupt event from the IEEE 1588 module. This bit |
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| should be used in conjunction with the 1588 Interrupt Status and Enable |
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| Register (1588_INT_STS_EN) to determine the source of the interrupt |
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| event within the 1588 module. |
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28 | Switch Fabric Interrupt Event (SWITCH_INT) | RO | 0b |
| This bit indicates an interrupt event from the Switch Fabric. This bit should |
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| be used in conjunction with the Switch Global Interrupt Pending Register |
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| (SW_IPR) to determine the source of the interrupt event within the Switch |
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| Fabric. |
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27 | Port 2 PHY Interrupt Event (PHY_INT2) | RO | 0b |
| This bit indicates an interrupt event from the Port 2 PHY. The source of the |
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| interrupt can be determined by polling the Port x PHY Interrupt Source |
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26 | Port 1 PHY Interrupt Event (PHY_INT1) | RO | 0b |
| This bit indicates an interrupt event from the Port 1 PHY. The source of the |
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| interrupt can be determined by polling the Port x PHY Interrupt Source |
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25 | TX Stopped (TXSTOP_INT) | R/WC | 0b |
| This interrupt is issued when STOP_TX bit in Transmit Configuration |
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| Register (TX_CFG) is set, and the Host MAC transmitter is halted. |
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24 | RX Stopped (RXSTOP_INT) | R/WC | 0b |
| This interrupt is issued when the Host MAC receiver is halted. |
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23 | RX Dropped Frame Counter Halfway (RXDFH_INT) | R/WC | 0b |
| This interrupt is issued when the Host MAC RX Dropped Frames Counter |
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| Register (RX_DROP) counts past its halfway point (7FFFFFFFh to |
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| 80000000h). |
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22 | RESERVED | RO | - |
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21 | TX IOC Interrupt (TX_IOC) | R/WC | 0b |
| This interrupt is generated when a buffer with the IOC flag set has been |
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| fully loaded into the TX Data FIFO. |
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20 | RX DMA Interrupt (RXD_INT) | R/WC | 0b |
| This interrupt is issued when the amount of data programmed in the RX |
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| DMA Count (RX_DMA_CNT) field of the Receive Configuration Register |
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| (RX_CFG) has been transferred out of the RX Data FIFO. |
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SMSC LAN9311/LAN9311i | 175 | Revision 1.4 |
| DATASHEET |
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