Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Datasheet

14.5.3.20Switch Engine Priority to Queue Register (SWE_PRI_TO_QUE)

Register #:

1845h

Size:

32 bits

This register specifies the Traffic Class table that maps the packet priority into the egress queues.

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

31:16

RESERVED

RO

-

 

 

 

 

15:14

Priority 7 traffic Class

R/W

11b

 

These bits specify the egress queue that is used for packets with a priority

 

 

 

of 7.

 

 

 

 

 

 

13:12

Priority 6 traffic Class

R/W

11b

 

These bits specify the egress queue that is used for packets with a priority

 

 

 

of 6.

 

 

 

 

 

 

11:10

Priority 5 traffic Class

R/W

10b

 

These bits specify the egress queue that is used for packets with a priority

 

 

 

of 5.

 

 

 

 

 

 

9:8

Priority 4 traffic Class

R/W

10b

 

These bits specify the egress queue that is used for packets with a priority

 

 

 

of 4.

 

 

 

 

 

 

7:6

Priority 3 traffic Class

R/W

01b

 

These bits specify the egress queue that is used for packets with a priority

 

 

 

of 3.

 

 

 

 

 

 

5:4

Priority 2 traffic Class

R/W

00b

 

These bits specify the egress queue that is used for packets with a priority

 

 

 

of 2.

 

 

 

 

 

 

3:2

Priority 1 traffic Class

R/W

00b

 

These bits specify the egress queue that is used for packets with a priority

 

 

 

of 1.

 

 

 

 

 

 

1:0

Priority 0 traffic Class

R/W

01b

 

These bits specify the egress queue that is used for packets with a priority

 

 

 

of 0.

 

 

 

 

 

 

Revision 1.4 (08-19-08)

390

SMSC LAN9311/LAN9311i

 

DATASHEET