Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Datasheet

14.2.8.5Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV)

Offset:

1D0h

Size:

32 bits

Index (decimal):

4

 

 

This read/write register contains the advertised ability of the Virtual PHY and is used in the Auto- Negotiation process with the link partner.

Note: This register is re-written in its entirety by the EEPROM Loader following the release or reset or a RELOAD command. Refer to Section 10.2.4, "EEPROM Loader," on page 150 for more information.

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

31:16

RESERVED

RO

-

 

(See Note 14.27)

 

 

 

 

 

 

15

Next Page

RO

0b

 

This bit determines the advertised next page capability and is always 0.

 

Note 14.28

 

0: Virtual PHY does not advertise next page capability

 

 

 

1: Virtual PHY advertises next page capability

 

 

 

 

 

 

14

RESERVED

RO

-

 

 

 

 

13

Remote Fault

RO

0b

 

This bit is not used since there is no physical link partner.

 

Note 14.29

 

 

 

 

12

RESERVED

RO

-

 

 

 

 

11

Asymmetric Pause

R/W

0b

 

This bit determines the advertised asymmetric pause capability.

 

 

 

0: No Asymmetric PAUSE toward link partner advertised

 

 

 

1: Asymmetric PAUSE toward link partner advertised

 

 

 

 

 

 

10

Pause

R/W

Note 14.30

 

This bit determines the advertised symmetric pause capability.

 

 

 

0: No Symmetric PAUSE toward link partner advertised

 

 

 

1: Symmetric PAUSE toward link partner advertised

 

 

 

 

 

 

9

100BASE-T4

RO

0b

 

This bit determines the advertised 100BASE-T4 capability and is always 0.

 

Note 14.31

 

0: 100BASE-T4 ability not advertised

 

 

 

1: 100BASE-T4 ability advertised

 

 

 

 

 

 

8

100BASE-X Full Duplex

R/W

1b

 

This bit determines the advertised 100BASE-X full duplex capability.

 

 

 

0: 100BASE-X full duplex ability not advertised

 

 

 

1: 100BASE-X full duplex ability advertised

 

 

 

 

 

 

7

100BASE-X Half Duplex

R/W

1b

 

This bit determines the advertised 100BASE-X half duplex capability.

 

 

 

0: 100BASE-X half duplex ability not advertised

 

 

 

1: 100BASE-X half duplex ability advertised

 

 

 

 

 

 

6

10BASE-T Full Duplex

R/W

1b

 

This bit determines the advertised 10BASE-T full duplex capability.

 

 

 

0: 10BASE-T full duplex ability not advertised

 

 

 

1: 10BASE-T full duplex ability advertised

 

 

 

 

 

 

SMSC LAN9311/LAN9311i

253

Revision 1.4 (08-19-08)

 

DATASHEET