Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Datasheet

For a transmission, the switch fabric MAC drives the transmit data onto the internal MII TXD bus and asserts TXEN to indicate valid data. The data is in the form of 4-bit wide data at a rate of 25MHz for 100BASE-TX, or 2.5MHz for 10BASE-T.

For reception, the 4-bit data nibbles are sent to the MII MAC Interface block. These data nibbles are clocked to the controller at a rate of 25MHz for 100BASE-TX, or 2.5MHz for 10BASE-T. RXCLK is the output clock for the internal MII bus. It is recovered from the received data to clock the RXD bus. If there is no received signal, it is derived from the system reference clock.

7.2.8PHY Management Control

The PHY Management Control block is responsible for the management functions of the PHY, including register access and interrupt generation. A Serial Management Interface (SMI) is used to support registers 0 through 6 as required by the IEEE 802.3 (Clause 22), as well as the vendor specific registers allowed by the specification. The SMI interface consists of the MII Management Data (MDIO) signal and the MII Management Clock (MDC) signal. These signals interface to the Host MAC and allow access to all PHY registers. Refer to Section 14.4.2, "Port 1 & 2 PHY Registers," on page 287 for a list of all supported registers and register descriptions. Non-supported registers will be read as FFFFh.

7.2.8.1PHY Interrupts

The PHY contains the ability to generate various interrupt events as described in Table 7.3. Reading the Port x PHY Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x) shows the source of the interrupt, and clears the interrupt signal. The Port x PHY Interrupt Mask Register (PHY_INTERRUPT_MASK_x) enables or disables each PHY interrupt. The PHY Management Control block aggregates the enabled interrupts status into an internal signal which is sent to the System Interrupt Controller and is reflected via the Interrupt Status Register (INT_STS) bit 26 (PHY_INT1) for the Port 1 PHY, and bit 27 (PHY_INT2) for the Port 2 PHY. For more information on the LAN9311/LAN9311i interrupts, refer to Chapter 5, "System Interrupts," on page 49.

Table 7.3 PHY Interrupt Sources

 

PHY_INTERRUPT_MASK_x &

INTERRUPT SOURCE

PHY_INTERRUPT_SOURCE_x REGISTER BIT #

 

 

ENERGYON Activated

7

 

 

Auto-Negotiation Complete

6

 

 

Remote Fault Detected

5

 

 

Link Down (Link Status Negated)

4

 

 

Auto-Negotiation LP Acknowledge

3

 

 

Parallel Detection Fault

2

 

 

Auto-Negotiation Page Received

1

 

 

7.2.9PHY Power-Down Modes

There are two power-down modes for the PHY:

„PHY General Power-Down

„PHY Energy Detect Power-Down

Note: For more information on the various power management features of the LAN9311/LAN9311i, refer to Section 4.3, "Power Management," on page 46.

Revision 1.4 (08-19-08)

94

SMSC LAN9311/LAN9311i

 

DATASHEET