SMSC LAN9311, LAN9311i 14.2.5.161588 Clock Target High-DWORDRegister (1588_CLOCK_TARGET_HI)

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Datasheet

14.2.5.161588 Clock Target High-DWORD Register (1588_CLOCK_TARGET_HI)

Offset: 17Ch Size: 32 bits

This read/write register combined with 1588 Clock Target Low-DWORD Register (1588_CLOCK_TARGET_LO) form the 64-bit 1588 Clock Target value. The 1588 Clock Target value is compared to the current 1588 Clock value and can be used to trigger an interrupt upon at match. Refer to Chapter 11, "IEEE 1588 Hardware Time Stamp Unit," on page 155 for additional information.

BITS	DESCRIPTION	TYPE	DEFAULT
31:0	Clock Target High (CLOCK_TARGET_HI)	R/W	00000000h
	This field contains the high 32-bits of the 64-bit 1588 Clock Compare value.

Note: Both this register and the 1588 Clock Target Low-DWORD Register (1588_CLOCK_TARGET_LO) must be written for either to be affected.

SMSC LAN9311/LAN9311i	217	Revision 1.4 (08-19-08)
	DATASHEET