Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Datasheet

14.5.3.17Switch Engine Port Ingress Configuration Register (SWE_PORT_INGRSS_CFG)

Register #:

1841h

Size:

32 bits

This register is used to configure the per port ingress rules.

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

31:6

RESERVED

RO

-

 

 

 

 

5:3

Enable Learning on Ingress

R/W

111b

 

When set, source addresses are learned when a packet is received on the

 

 

 

corresponding port and the corresponding Port State in the Switch Engine

 

 

 

Port State Register (SWE_PORT_STATE) is set to forwarding or learning.

 

 

 

There is one enable bit per ingress port. Bits 5,4,3 correspond to switch

 

 

 

ports 2,1,0 respectively.

 

 

 

 

 

 

2:0

Enable Membership Checking

R/W

000b

 

When set, VLAN membership is checked when a packet is received on the

 

 

 

corresponding port.

 

 

 

The packet will be filtered if the ingress port is not a member of the VLAN

 

 

 

(unless the Admit Non Member bit is set for the port in the Switch Engine

 

 

 

Admit Non Member Register (SWE_ADMT_N_MEMBER))

 

 

 

For destination addresses that are found in the ALR table, the packet will be

 

 

 

filtered if the egress port is not a member of the VLAN (for destination

 

 

 

addresses that are not found in the ALR table only the ingress port is

 

 

 

checked for membership).

 

 

 

The VLAN Enable bit in the Switch Engine Global Ingress Configuration

 

 

 

Register (SWE_GLOBAL_INGRSS_CFG) needs to be set for these bits to

 

 

 

have an affect.

 

 

 

There is one enable bit per ingress port. Bits 2,1,0 correspond to switch

 

 

 

ports 2,1,0 respectively.

 

 

 

 

 

 

SMSC LAN9311/LAN9311i

387

Revision 1.4 (08-19-08)

 

DATASHEET