Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Datasheet

14.2.8.3Virtual PHY Identification MSB Register (VPHY_ID_MSB)

Offset:

1C8h

Size:

32 bits

Index (decimal):

2

 

 

This read/write register contains the MSB of the Virtual PHY Organizationally Unique Identifier (OUI). The LSB of the Virtual PHY OUI is contained in the Virtual PHY Identification LSB Register (VPHY_ID_LSB).

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

31:16

RESERVED

RO

-

 

(See Note 14.23)

 

 

 

 

 

 

15:0

PHY ID

R/W

0000h

 

This field contains the MSB of the Virtual PHY OUI (Note 14.24).

 

 

 

 

 

 

Note 14.23 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on a DWORD boundary. When accessed serially (through the MII management protocol), the register is 16-bits wide.

Note 14.24 IEEE allows a value of zero in each of the 32-bits of the PHY Identifier.

SMSC LAN9311/LAN9311i

251

Revision 1.4 (08-19-08)

 

DATASHEET