Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Datasheet

14.2.9Miscellaneous

This section details the remainder of the System CSR’s. These registers allow for monitoring and configuration of various LAN9311/LAN9311i functions such as the Chip ID/revision, byte order testing, power management, hardware configuration, general purpose timer, and free running counter.

14.2.9.1Chip ID and Revision (ID_REV)

Offset:

050h

Size:

32 bits

This read-only register contains the ID and Revision fields for the LAN9311/LAN9311i.

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

31:16

Chip ID

RO

9311h

 

This field indicates the chip ID.

 

 

 

 

 

 

15:0

Chip Revision

RO

Note 14.46

 

This field indicates the design revision.

 

 

 

 

 

 

 

Note 14.46 Default value is dependent on device revision.

 

 

Revision 1.4 (08-19-08)

260

SMSC LAN9311/LAN9311i

 

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