Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

 

 

Datasheet

 

Table 14.7 Port 1 & 2 PHY MII Serially Adressable Registers (continued)

 

 

 

INDEX #

SYMBOL

REGISTER NAME

 

 

 

17

PHY_MODE_CONTROL_STATUS_x

Port x PHY Mode Control/Status Register, Section 14.4.2.8

 

 

 

18

PHY_SPECIAL_MODES_x

Port x PHY Special Modes Register, Section 14.4.2.9

 

 

 

27

PHY_SPECIAL_CONTROL_STAT_IND_x

Port x PHY Special Control/Status Indication Register,

 

 

Section 14.4.2.10

 

 

 

29

PHY_INTERRUPT_SOURCE_x

Port x PHY Interrupt Source Flags Register, Section 14.4.2.11

 

 

 

30

PHY_INTERRUPT_MASK_x

Port x PHY Interrupt Mask Register, Section 14.4.2.12

 

 

 

31

PHY_SPECIAL_CONTROL_STATUS_x

Port x PHY Special Control/Status Register, Section 14.4.2.13

 

 

 

Revision 1.4 (08-19-08)

288

SMSC LAN9311/LAN9311i

 

DATASHEET