Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Datasheet

15.6Clock Circuit

The LAN9311/LAN9311i can accept either a 25MHz crystal (preferred) or a 25MHz single-ended clock oscillator (+/- 50ppm) input. If the single-ended clock oscillator method is implemented, XO should be left unconnected and XI should be driven with a nominal 0-3.3V clock signal. The input clock duty cycle is 40% minimum, 50% typical and 60% maximum.

It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals (XI/XO). See Table 15.15 for crystal specifications.

Table 15.15 LAN9311/LAN9311iCrystal Specifications

PARAMETER

SYMBOL

MIN

 

NOM

 

MAX

UNITS

NOTES

 

 

 

 

 

 

 

 

 

Crystal Cut

 

 

 

AT, typ

 

 

 

 

 

 

 

 

 

 

Crystal Oscillation Mode

 

 

Fundamental Mode

 

 

 

 

 

 

 

 

Crystal Calibration Mode

 

Parallel Resonant Mode

 

 

 

 

 

 

 

 

 

 

 

Frequency

Ffund

-

 

25.000

 

-

MHz

 

Frequency Tolerance @ 25oC

Ftol

-

 

-

 

+/-50

PPM

Note 15.12

Frequency Stability Over Temp

Ftemp

-

 

-

 

+/-50

PPM

Note 15.12

Frequency Deviation Over Time

Fage

-

 

+/-3 to 5

 

-

PPM

Note 15.13

Total Allowable PPM Budget

 

-

 

-

 

+/-50

PPM

Note 15.14

 

 

 

 

 

 

 

 

 

Shunt Capacitance

CO

-

 

7 typ

 

-

pF

 

Load Capacitance

CL

-

 

20 typ

 

-

pF

 

Drive Level

PW

300

 

-

 

-

uW

 

Equivalent Series Resistance

R1

-

 

-

 

30

Ohm

 

Operating Temperature Range

 

0

 

-

 

+70Note 1

oC

 

 

 

 

 

 

 

5.16

 

 

 

 

 

 

 

 

 

 

 

n/a XI Pin Capacitance

 

-

 

3 typ

 

-

pF

Note 15.15

 

 

 

 

 

 

 

 

 

n/a XO Pin Capacitance

 

-

 

3 typ

 

-

pF

Note 15.15

 

 

 

 

 

 

 

 

 

Note 15.12 The maximum allowable values for Frequency Tolerance and Frequency Stability are application dependant. Since any particular application must meet the IEEE +/-50 PPM Total PPM Budget, the combination of these two values must be approximately +/-45 PPM (allowing for aging).

Note 15.13 Frequency Deviation Over Time is also referred to as Aging.

Note 15.14 The total deviation for the Transmitter Clock Frequency is specified by IEEE 802.3 as +/- 50 PPM.

Note 15.15 This number includes the pad, the bond wire and the lead frame. PCB capacitance is not included in this value. The XO/XI pin and PCB capacitance values are required to accurately calculate the value of the two external load capacitors. These two external load capacitors determine the accuracy of the 25.000 MHz frequency.

Note 15.16 +70oC for commercial version (LAN9311), +85oC for industrial version (LAN9311I)

SMSC LAN9311/LAN9311i

455

Revision 1.4 (08-19-08)

 

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