Two Port 10/100 Managed Ethernet Switch with
Datasheet
14.2.7.2PHY Management Interface Access Register (PMI_ACCESS)Offset: | 0A8h | Size: | 32 bits |
| EEPROM Loader |
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| Access Only |
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This register is used to control the management cycles to the PHYs. A PHY access is initiated when this register is written. This register is used in conjunction with the PHY Management Interface Data Register (PMI_DATA) to perform write operations to the PHYs.
Note: This register is only accessible by the EEPROM Loader and NOT by the Host bus. Refer to Section 10.2.4, "EEPROM Loader," on page 150 for additional information.
BITS | DESCRIPTION | TYPE | DEFAULT |
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31:16 | RESERVED | RO | - |
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15:11 | PHY Address (PHY_ADDR) |
| 00000b |
| These bits select the PHY device being accessed. Refer to Section 7.1.1, | WO |
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| "PHY Addressing," on page 82 for information on PHY address |
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| assignments. |
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10:6 | MII Register Index (MIIRINDA) |
| 00000b |
| These bits select the desired MII register in the PHY. Refer to Section 14.4, | WO |
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| "Ethernet PHY Control and Status Registers," on page 287 for detailed |
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| descriptions on all PHY registers. |
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5:2 | RESERVED | RO | - |
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1 | RESERVED | WO | 0b |
| Note: This bit must always be written with a value of 1. |
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0 | RESERVED | RO | 0b |
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SMSC LAN9311/LAN9311i | 245 | Revision 1.4 |
| DATASHEET |
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