Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Datasheet

BITS

 

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

9

Wake-On-LAN Enable (WOL_EN)

R/W

0b

 

When set, the PME signal (if enabled via the PME_EN bit) will be asserted

 

 

 

in accordance with the PME_IND bit upon a WOL event. When set, the

 

 

 

PME_INT bit in the Interrupt Status Register (INT_STS) will also be asserted

 

 

 

upon a WOL event, regardless of the setting of the PME_EN bit.

 

 

 

 

 

 

8:7

RESERVED

RO

-

 

 

 

 

6

PME Buffer Type (PME_TYPE)

R/W

0b

 

When this bit is cleared, the PME pin functions as an open-drain buffer for

NASR

 

 

use in a wired-or configuration. When set, the PME pin is a push-pull driver.

 

 

 

Note:

When PME is configured as an open-drain output, the PME_POL

 

 

 

 

field of this register is ignored and the output is always active low.

 

 

 

0: PME pin open-drain output

 

 

 

1: PME pin push-pull driver

 

 

 

 

 

 

5

Wake On LAN Status (WOL_STS)

R/WC

0b

 

This bit indicates that a wake-up frame or magic packet was detected by the

 

 

 

Host MAC.

 

 

 

In order to clear this bit, it is required that the event in the Host MAC be

 

 

 

cleared as well. The event sources are described in Section 4.3, "Power

 

 

 

Management," on page 46.

 

 

 

 

 

 

4

RESERVED

RO

-

 

 

 

 

3

PME Indication (PME_IND)

R/W

0b

 

The PME signal can be configured as a pulsed output or a static signal,

 

 

 

which is asserted upon detection of a wake-up event. When set, the PME

 

 

 

signal will pulse active for 50mS upon detection of a wake-up event. When

 

 

 

cleared, the PME signal is driven continuously upon detection of a wake-up

 

 

 

event.

 

 

 

 

0: PME 50mS pulse on detection of event

 

 

 

1: PME driven continuously on detection of event

 

 

 

The PME signal can be deactivated by clearing the WOL_STS bit or by

 

 

 

clearing the appropriate enable.

 

 

 

 

 

 

2

PME Polarity (PME_POL)

R/W

0b

 

This bit controls the polarity of the PME signal. When set, the PME output

NASR

 

 

is an active high signal. When cleared, it is active low.

 

 

 

Note:

When PME is configured as an open-drain output, this field is

 

 

 

 

ignored and the output is always active low.

 

 

 

0: PME active low

 

 

 

1: PME active high

 

 

 

 

 

 

1

PME Enable (PME_EN)

R/W

0b

 

When set, this bit enables the external PME signal pin. When cleared, the

 

 

 

external PME signal is disabled.

 

 

 

Note:

This bit does not affect the PME_INT interrupt bit of the Interrupt

 

 

 

 

Status Register (INT_STS).

 

 

 

0: PME pin disabled

 

 

 

1: PME pin enabled

 

 

 

 

 

 

 

SMSC LAN9311/LAN9311i

265

Revision 1.4 (08-19-08)

 

DATASHEET