Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Datasheet

14.2.9.2Byte Order Test Register (BYTE_TEST)

Offset:

064h

Size:

32 bits

This read-only register can be used to determine the byte ordering of the current configuration. Byte ordering is a function of the host data bus width and endianess. Refer to Section 8.3, "Host Data Bus," on page 99 and Section 8.4, "Host Endianess," on page 100 for additional information on byte ordering.

Note: This register can be read while the LAN9311/LAN9311i is in the reset or not ready states.

Note: Either half of this register can be read without the need to read the other half.

The BYTE_TEST register can optionally be used as a dummy read register when assuring minimum write-to-read or read-to-read timing. Refer to Section 8.5.2, "Special Restrictions on Back-to Back Write-Read Cycles," on page 102 and Section 8.5.3, "Special Restrictions on Back-to-Back Read Cycles," on page 106 for additional information.

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

31:0

Byte Test (BYTE_TEST)

RO

87654321h

 

This field reflects the current byte ordering

 

 

 

 

 

 

SMSC LAN9311/LAN9311i

261

Revision 1.4 (08-19-08)

 

DATASHEET