Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Datasheet

14.5.2.44Port x MAC Interrupt Pending Register (MAC_IPR_x)

Register #:

Port0: 0481h

Size:

32 bits

 

Port1:

0881h

 

 

 

Port2:

0C81h

 

 

This read-only register contains the pending Port x interrupts. A set bit indicates an interrupt has been triggered. All interrupts in this register may be masked via the Port x MAC Interrupt Pending Register (MAC_IPR_x) register. Refer to Chapter 5, "System Interrupts," on page 49 for more information.

Note: There are no possible Port x interrupt conditions available. This register exists for future use.

BITS

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

31:0

RESERVED

RO

-

 

 

 

 

SMSC LAN9311/LAN9311i

367

Revision 1.4 (08-19-08)

 

DATASHEET