Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Datasheet

BITS

 

DESCRIPTION

TYPE

DEFAULT

 

 

 

 

0

Device Ready (READY)

RO

0b

 

When set, this bit indicates that the LAN9311/LAN9311i is ready to be

 

 

 

accessed. Upon power-up, nRST reset, soft reset, or digital reset, the host

 

 

 

processor may interrogate this field as an indication that the

 

 

 

LAN9311/LAN9311i has stabilized and is fully active.

 

 

 

This bit can cause an interrupt if enabled.

 

 

 

Note:

With the exception of the HW_CFG, PMT_CTRL, BYTE_TEST, and

 

 

 

 

RESET_CTL registers, read access to any internal resources is

 

 

 

 

forbidden while the READY bit is cleared. Writes to any address

 

 

 

 

are invalid until this bit is set.

 

 

 

Note:

This bit is identical to bit 27 of the Hardware Configuration Register

 

 

 

 

(HW_CFG)

 

 

 

 

 

 

 

Revision 1.4 (08-19-08)

266

SMSC LAN9311/LAN9311i

 

DATASHEET