Xantrex Technology XG 850 manual Status Registers Model from Ieee

Status Registers Model from IEEE 488.2

Status Registers Model from IEEE 488.2

The IEEE 488.2 registers shown in the bottom rectangle of Figure 5-16 follow the IEEE 488.2 model for status registers. The IEEE 488.2 register only has enable registers for masking the summary bits. Figure 5-17 shows the details on the relationship between the mask/enable registers and the summary bits. Sections describing the bits for both registers will follow Figure 5-17.

Error/Event Queue Status Flag

QUEStionable SCPI Register

Summary Bit

OPERational SCPI Register

Summary Bit

Standard

Event Status

	Register
	(SESR)		SESR
			Summary
	0	&	Bit
	1	&
	2	&
...	3	&	+
	4		&
	5		&
	6		&
	7		&
	SERS Enable
	Register
	0
	1
	2
	3
	4
	5
	6
	7
Figure 5-17		IEEE 488.2 Register Model

Status Byte		MSS
Register
		Summary
		Bit
0	&
1	&
2	&	+
3		&
4		&
5		&
6
7		&
Status Byte		5
Enable Register
0
1
2
3
4
5
6
7

M370078-01 5-27