Intel® NetStructureTMZT 7102 Chassis Management Module

Hardware Specifications

Table 6. J2 Connector Pinout

Pin#

A

B

C

D

E

F

 

 

 

 

 

 

 

11

N_SCL1

N_SDA1

N_SCL10

N_SDA10

N_SCL18

 

 

 

 

 

 

 

 

10

N_SCL2

N_SDA2

N_SCL11

N_SDA11

N_SDA18

 

 

 

 

 

 

 

 

9

N_SCL3

N_SDA3

N_SCL12

N_SDA12

N_SCL19

 

 

 

 

 

 

 

 

8

N_SCL4

N_SDA4

N_SCL13

N_SDA13

N_SDA19

 

 

 

 

 

 

 

 

7

N_SCL5

N_SDA5

N_SCL14

N_SDA14

N_SCL20

 

 

 

 

 

 

 

GROUND

6

N_SCL6

N_SDA6

N_SCL15

N_SDA15

N_SDA20

SHIELD

 

 

 

 

 

 

5

N_SCL7

N_SDA7

N_SCL16

N_SDA16

N_SCL21

 

 

 

 

 

 

 

 

4

N_SCL8

N_SDA8

N_SCL17

N_SDA17

N_SDA21

 

 

 

 

 

 

 

 

3

N_SCL9

N_SDA9

GND

NEG_O

HLY_O#

 

 

 

 

 

 

 

 

2

R_SCL

IPMB_PWR

RES

IPMB_PWR

HLY_I#

 

1

GND

R_SDA

CMM_SEL#

NEG_I

GND

 

 

 

 

 

 

 

 

NOTE: # Designates a low true signal.

All signals interface to medium length pins on the backplane except as noted.

= Interfaces to long connector pins on the backplane. = Interfaces to short connector pins on the backplane.

2.8.3J3 Backplane Connector

J3 is a 55-contact 2 mm x 2 mm female CompactPCI form-factor connector (AMP 352115-1). See Table 7 for pin definitions and Figure 6 for relative pin placement.

Table 7. J3 Connector Pinout

Pin#

A

B

C

D

E

F

 

 

 

 

 

 

 

 

11

N_HLY1#

N_BDS1#

N_HLY10#

N_BDS10#

N_HLY18#

 

 

 

 

 

 

 

 

 

10

N_HLY2#

N_BDS2#

N_HLY11#

N_BDS11#

N_BDS18#

 

 

 

 

 

 

 

 

 

9

N_HLY3#

N_BDS3#

N_HLY12#

N_BDS12#

N_HLY19#

 

 

 

 

 

 

 

 

 

8

N_HLY4#

N_BDS4#

N_HLY13#

N_BDS13#

N_BDS19#

 

 

 

 

 

 

 

 

 

7

N_HLY5#

N_BDS5#

N_HLY14#

N_BDS14#

N_HLY20#

 

 

 

 

 

 

 

 

GROUND

6

N_HLY6#

N_BDS6#

N_HLY15#

N_BDS15#

N_BDS20#

SHIELD

 

 

 

 

 

 

 

5

N_HLY7#

N_BDS7#

N_HLY16#

N_BDS16#

N_HLY21#

 

 

 

 

 

 

 

 

 

4

N_HLY8#

N_BDS8#

N_HLY17#

N_BDS17#

N_BDS21#

 

 

 

 

 

 

 

 

 

3

N_HLY9#

N_BDS9#

IPMB_PWR

PIMP0#

RES

 

 

 

 

 

 

 

 

 

2

RES

GND

RES

GND

RES

 

1

IPMB_PWR

RES

PRES_O#

PIMP1#

IPMB_PWR

 

 

 

 

 

 

 

 

 

NOTE: # Designates a low true signal.

All signals interface to medium length pins on the backplane except as noted.

= Interfaces to long connector pins on the backplane. = Interfaces to short connector pins on the backplane.

Technical Product Specification

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Intel ZT 7102 manual 3 J3 Backplane Connector, J2 Connector Pinout, J3 Connector Pinout