Intel ZT 7102 manual Bist Test Descriptions

Intel® NetStructureTMZT 7102 Chassis Management Module

Built-In Self Test

6.8BIST Test Descriptions

6.8.1Flash Checksum Test

This test is targeted to verify the RedBoot image and FPGA image are not corrupted.This test will calculate the CRC32 checksum from the RedBoot image, and then compare with the image checksum stored in the FIS directory. If one mismatches another, BIST will switch to the backup image. If checksum mismatch was found from the FPGA image, BIST will load the backup image to program the FPGA device.

6.8.2Base Memory Test

This test will write the data pattern of 55AA55AA into every 4-byte of memory below 1 Mbyte. Its objective is to verify wire connectivity of address and data pins between the memory module and the processor. The test will write the data pattern into the complete first 1 Mbyte, then verify the written data pattern by reading them out from the memory module. If the data pattern mismatches, the test will log the error event into event-log area and route error message to serial port.

6.8.3Extended Memory Tests

6.8.3.1Walking Ones Test

This test is targeted to verify the data bus wiring by testing the bus one bit at a time. The data bus passes the test if each data bit can be set to 0 and 1 independently of the other data bits.

6.8.3.232-Bit Address Test

This test is targeted to verify the address bus wiring. The smallest set of addresses that will cover all possible combinations is the set of “power-of-two” addresses. These addresses are analogous to the set of data values used in the walking 1's test. The corresponding memory locations are 0001h, 0002h, 0004h, 0008h, 0010h, 0020h, and so on. In addition, address 0000h must also be tested. The possibility of overlapping locations makes the address bus test harder to implement. After writing to one of the addresses, we must check that none of the others has been overwritten.

Note that not all of the address lines can be tested in this way. Part of the address-the left most bits-selects the memory chip itself. Another part-the right most bits-may not be significant if the data bus width is greater than eight bits. These extra bits will remain constant throughout the test and reduce the number of test addresses. For example, if the processor has 32 address bits, it can address up to 4 Gbytes of memory. If we want to test a 128 Kbyte block of memory, the 15 most-significant address bits will remain constant. In that case, only the 17 rightmost bits of the address bus can actually be tested. (128 K is 1/32,768th of the total 4 Gbyte address space.)

To confirm that no two memory locations overlap, first write some initial data value at each power-of-two offset within the device. Then a new value is written-an inverted copy of the initial value, to the first test offset. It is then verified that the initial data value is still stored at every other power-of-two offset. If a location is found, other than the one just written, that contains the new data value, you have found a problem with the current address bit. If no overlapping is found, the procedure is repeated for each of the remaining offsets.

6.8.3.332-Bit Inverse Address Test

This test is similar to the 32-bit address test except the addresses are tested in the inverse direction. The test helps identify a broader scope of possible addressing errors inherent in memory modules.

Technical Product Specification 51