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Intel® NetStructureTMZT 7102 Chassis Management Module
Hardware Specifications
2.8.4Backplane Pin Descriptions
Table 8. Pin Type Definitions
Pin Type | Definition |
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OD | Open Drain |
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I | Input |
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I/O | Input/Output |
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O | Output |
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Table 9. Pin Descriptions (Sheet 1 of 2)
Name | Count | Type | Description | |
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N_SCL[1..21] | 21 | OD | Node IPMI clock | |
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N_SDA[1..21] | 21 | OD | Node IMPI data | |
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PS_SCL[0..1] | 2 | OD | Power Supply Chassis IMPI clock | |
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PS_SDA[0..1] | 2 | OD | Power Supply Chassis IMPI data | |
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FT_SCL | 1 | OD | Fan Tray Chassis IMPI clock | |
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FT_SDA | 1 | OD | Fan Tray Chassis IMPI data | |
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CS_SCL | 1 | OD | Chassis Sensor IMPI clock | |
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CS_SDA | 1 | OD | Chassis Sensor IMPI data | |
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CF_SCL[0..1] | 2 | OD | Chassis FRU IMPI clock | |
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CF_SDA[0..1] | 2 | OD | Chassis FRU IMPI data | |
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R_SCL | 1 | OD | Redundant CMM serial clock | |
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R_SDA | 1 | OD | Redundant CMM serial data | |
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N_HLY#[1..21] | 21 | I | Node Healthy (0 = Node is healthy) | |
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N_BDS#[1..21] | 21 | OD | Node Board Select (5 V = Node is present, drive to 0 | |
I/O | to turn node on) | |||
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2 | I/O | 10/100 Ethernet To Switch | ||
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2 | I/O | 10/100 Ethernet From Switch | ||
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FANTK[0..15] | 16 | I | Fan Tach Inputs | |
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FANPWM[0..3] | 4 | O | Fan Speed Control (3.3 V = ON) | |
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FANP#[0..3] | 4 | I | Fan tray present (3.3 V = fan tray is missing) | |
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PDEG#[0..7] | 8 | I | Power supply degrade | |
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PFAIL#[0..7] | 8 | I | Power supply fail | |
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PINH#[0..7] | 8 | O | Power supply inhibit | |
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STx | 1 | O | Serial transmit | |
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SRx | 1 | I | Serial receive | |
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SCTS | 1 | I | Serial clear to send | |
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SRTS | 1 | O | Serial request to send | |
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SDSR | 1 | I | Serial data set ready | |
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26 | Technical Product Specification |