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Intel® NetStructureTMZT 7102 Chassis Management Module
6.8.4FPGA Version Check
This test is targeted to verify the correct FPGA image programmed into both FPGA chips. This test will display the FPGA version on both FPGAs. Both versions should be the same, or the user will be prompted with a warning message. If the programmed version is older than the expected, user will be prompted to upgrade to the latest FPGA image.
6.8.5DS1307 RTC Test
This test is targeted to verify the functionality of DS1307 RTC chip. This test will display the date/time settings from the RTC and validate the readings. If any readings found to be
6.8.6NIC Presence/Local PCI Bus Test
This test generates the PCI bus transaction by scanning the PCI buses available on the board. This test will detect the two Ethernet devices and verify each device has the valid Vendor ID and Device ID in the PCI configuration space. NIC internal
6.8.7OS Image Checksum Test
This test is targeted to verify the OS image stored in the flash is not corrupted. This test will calculate the CRC32 checksum from the OS image, then compare with the image checksum stored in the FIS directory. If one mismatches the other, BIST will log an error event to the
6.8.8CRC32 Checksum
CRC32 is the
It first generates the diffusion table, which consists of 256 entries of
6.8.9IPMB Bus Busy/Not Ready Test
This test identifies any potential FPGA lockup before loading BlueCat. If the FPGA is detected to be locked up, an event indicating which bus actually failed will be logged into the Event log.
52 | Technical Product Specification |