Intel ZT 7102 manual Fpga Version Check, 5 DS1307 RTC Test, NIC Presence/Local PCI Bus Test

Intel® NetStructureTMZT 7102 Chassis Management Module

Built-In Self Test

6.8.4FPGA Version Check

This test is targeted to verify the correct FPGA image programmed into both FPGA chips. This test will display the FPGA version on both FPGAs. Both versions should be the same, or the user will be prompted with a warning message. If the programmed version is older than the expected, user will be prompted to upgrade to the latest FPGA image.

6.8.5DS1307 RTC Test

This test is targeted to verify the functionality of DS1307 RTC chip. This test will display the date/time settings from the RTC and validate the readings. If any readings found to be non-BCD format, user will be prompted with warning message. This test will also capture current time, sleep a while, then compare the previously captured time and new time. If they differ, it means the RTC is working. Otherwise, user will be prompted with warning message.

6.8.6NIC Presence/Local PCI Bus Test

This test generates the PCI bus transaction by scanning the PCI buses available on the board. This test will detect the two Ethernet devices and verify each device has the valid Vendor ID and Device ID in the PCI configuration space. NIC internal self-test will not be performed here, as the self-test will be executed when loading the Ethernet driver.

6.8.7OS Image Checksum Test

This test is targeted to verify the OS image stored in the flash is not corrupted. This test will calculate the CRC32 checksum from the OS image, then compare with the image checksum stored in the FIS directory. If one mismatches the other, BIST will log an error event to the event-log area and route the error message to serial port.

6.8.8CRC32 Checksum

CRC32 is the 32-bit version of Cyclic Redundant Check technique designed to ensure the bits’ validity and integrity within the data.

It first generates the diffusion table, which consists of 256 entries of double-word; each entry is known as a unique diffusion code. The checksum calculation is started by fetching the first byte in data buffer, exclusive-OR with the temporary checksum value. The resulting value will be AND-ed with 0xFF to restrict an index from 0 to 255 (decimal). That index will be used to fetch a new diffusion code from the table. Next, the newly fetched diffusion code will be exclusive-OR with the most significant 24 bits of the temporary checksum value (effectively 8 bits left-shifting the checksum value). The resulting value is the new temporary checksum value. The calculation process is repeated until the last byte in the data buffer. The final temporary checksum value becomes the final checksum value.

6.8.9IPMB Bus Busy/Not Ready Test

This test identifies any potential FPGA lockup before loading BlueCat. If the FPGA is detected to be locked up, an event indicating which bus actually failed will be logged into the Event log.

52 Technical Product Specification