Freescale Semiconductor MC9S12XDP512 3.3.2.2 RESERVED1, 3.3.2.3 RESERVED2

Chapter 3 4 Kbyte EEPROM Module (S12XEETX4KV2)
MC9S12XDP512 Data Sheet, Rev. 2.11
Freescale Semiconductor 149
All bits in the ECLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.
3.3.2.2 RESERVED1
This register is reserved for factory testing and is not accessible.
All bits read 0 and are not writable.
3.3.2.3 RESERVED2
This register is reserved for factory testing and is not accessible.
Module Base + 0x0000
76543210
R EDIVLD PRDIV8 EDIV5 EDIV4 EDIV3 EDIV2 EDIV1 EDIV0
W
Reset 00000000
= Unimplemented or Reserved
Figure 3-2. EEPROM Clock Divider Register (ECLKDIV)
Table 3-3. ECLKDIV Field Descriptions
Field Description
7
EDIVLD
Clock Divider Loaded
0 Register has not been written.
1 Register has been written to since the last reset.
6
PRDIV8
Enable Prescalar by 8
0 The oscillator clock is directly fed into the ECLKDIV divider.
1 Enables a Prescalar by 8, to divide the oscillator clock before feeding into the clock divider.
5–0
EDIV[5:0]
Clock Divider Bits — The combination of PRDIV8 and EDIV[5:0] effectively divides the EEPROM module input
oscillator clock down to a frequency of 150 kHz – 200 kHz. The maximum divide ratio is 512. Please refer to
Section 3.4.1.1, “Writing the ECLKDIV Register” for more information.
Module Base + 0x0001
76543210
R00000000
W
Reset 00000000
= Unimplemented or Reserved
Figure 3-3. RESERVED1