Freescale Semiconductor MC9S12XDP512 4.3.2.17 Port T Data Register (PTT), 4.3.2.18 Port T Input Register (PTIT)

Chapter 4 Port Integration Module (S12XDP512PIMV2)
MC9S12XDP512 Data Sheet, Rev. 2.11
Freescale Semiconductor 213
4.3.2.17 Port T Data Register (PTT)
Read: Anytime.
Write: Anytime.
4.3.2.18 Port T Input Register (PTIT)
Read: Anytime.
Write: Never, writes to this register have no effect.
0x0240
76543210
R
PTT7 PTT6 PTT5 PTT4 PTT3 PTT2 PTT1 PTT0
W
ECT IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0
Reset 00000000
Figure 4-19. Port T Data Register (PTT)
Table 4-21. PTT Field Descriptions
Field Description
7–0
PTT[7:0]
Port T — Port T bits 7–0 are associated with ECT channels IOC7–IOC0 (refer to ECT section). When not used
with the ECT, these pins can be used as general purpose I/O.
If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port
register, otherwise the buffered pin input state is read.
0x0241
76543210
R PTIT7 PTIT6 PTIT5 PTIT4 PTIT3 PTIT2 PTIT1 PTIT0
W
Reset1
1These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated
pin values.
————————
= Unimplemented or Reserved
Figure 4-20. Port T Input Register (PTIT)
Table 4-22. PTIT Field Descriptions
Field Description
7–0
PTIT[7:0]
Port T Input — This register always reads back the buffered state of the associated pins. This can also be used
to detect overload or short circuit conditions on output pins.