Chapter 9 XGATE (S12XGATEV2)
MC9S12XDP512 Data Sheet, Rev. 2.11
440 Freescale Semiconductor
Operation
RS2 – RS1 ⇒NONE (translates to SUB R0, RS1, RS2)
RD – IMM16 ⇒ NONE (translates to CMPL RD, #IMM16[7:0]; CPCH RD, #IMM16[15:8])
Subtracts two 16-bit values and discards the result.
CCR Effects
Code and CPU Cycles
CMP Compare CMP
NZVC
∆∆∆∆
N: Set if bit 15 of the result is set; cleared otherwise.
Z: Set if the result is $0000; cleared otherwise.
V: Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RS1[15] & RS2[15] & result[15] | RS1[15] & RS2[15] & result[15]
RD[15] & IMM16[15] & result[15] | RD[15] & IMM16[15] & result[15]
C: Set if there is a carry from the bit 15 of the result; cleared otherwise.
RS1[15] & RS2[15] | RS1[15] & result[15] | RS2[15] & result[15]
RD[15] & IMM16[15] | RD[15] & result[15] | IMM16[15] & result[15]
Source Form Address
Mode Machine Code Cycles
CMP RS1, RS2 TRI 0 0 0 1 1 0 0 0 RS1 RS2 0 0 P
CMP RS, #IMM16 IMM8 1 1 0 1 0 RS IMM16[7:0] P
IMM8 1 1 0 1 1 RS IMM16[15:8] P