Chapter 8 Analog-to-Digital Converter (ATD10B8CV3)
MC9S12XDP512 Data Sheet, Rev. 2.11
366 Freescale Semiconductor
8.3.2.10 ATD Status Register 1 (ATDSTAT1)

This read-only register contains the conversion complete flags.

Read: Anytime
Write: Anytime, no effect

Table 8-19. Special Channel Select Coding

SC CC CB CA Analog Input Channel
1 0 X X Reserved
11 0 0 V
RH
11 0 1 V
RL
11 1 0 (V
RH+VRL) / 2
1 1 1 1 Reserved
Module Base + 0x000B
76543210
R CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0
W
Reset 00000000
= Unimplemented or Reserved

Figure 8-12. ATD Status Register 1 (ATDSTAT1)

Table 8-20. ATDSTAT1 Field Descriptions

Field Description
7–0
CCF[7:0]
Conversion Complete Flag x (x = 7, 6, 5, 4, 3, 2, 1, 0) — A conversion complete flag is set at the end of each
conversion in a conversion sequence. The flags are associated with the conversion position in a sequence (and
also the result register number). Therefore, CCF0 is set when the first conversion in a sequence is complete and
the result is available in result register ATDDR0; CCF1 is set when the second conversion in a sequence is
complete and the result is available in ATDDR1, and so forth. A flag CCFx (x = 7, 6, 5, 4, 3, 2,1, 70) is cleared
when one of the following occurs:
A) Write to ATDCTL5 (a new conversion sequence is started)
B) If AFFC=0 and read of ATDSTAT1 followed by read of result register ATDDRx
C) If AFFC=1 and read of result register ATDDRx
In case of a concurrent set and clear on CCFx: The clearing by method A) will overwrite the set. The clearing by
methods B) or C) will be overwritten by the set.
0 Conversion number x not completed
1 Conversion number x has completed, result ready in ATDDRx