Freescale Semiconductor MC9S12XDP512 5.3.2.1 CRG Synthesizer Register (SYNR), 5.3.2.2 CRG Reference Divider Register (REFDV)

Chapter 5 Clocks and Reset Generator (S12CRGV6)
MC9S12XDP512 Data Sheet, Rev. 2.11
Freescale Semiconductor 277
5.3.2.1 CRG Synthesizer Register (SYNR)
The SYNR register controls the multiplication factor of the PLL. If the PLL is on, the count in the loop
divider (SYNR) register effectively multiplies up the PLL clock (PLLCLK) from the reference frequency
by 2 x (SYNR + 1). PLLCLK will not be below the minimum VCO frequency (fSCM).
NOTE
If PLL is selected (PLLSEL=1), Bus Clock = PLLCLK / 2
Bus Clock must not exceed the maximum operating system frequency.
Read: Anytime
Write: Anytime except if PLLSEL = 1
NOTE
Write to this register initializes the lock detector bit and the track detector
bit.
5.3.2.2 CRG Reference Divider Register (REFDV)
The REFDV register provides a finer granularity for the PLL multiplier steps. The count in the reference
divider divides OSCCLK frequency by REFDV + 1.
Read: Anytime
Write: Anytime except when PLLSEL = 1
Module Base +0x_00
76543210
R0 0 SYN5 SYN4 SYN3 SYN2 SYN1 SYN0
W
Reset 00000000
= Unimplemented or Reserved
Figure 5-4. CRG Synthesizer Register (SYNR)
Module Base +0x_01
76543210
R0 0 REFDV5 REFDV4 REFDV3 REFDV2 REFDV1 REFDV0
W
Reset 00000000
= Unimplemented or Reserved
Figure 5-5. CRG Reference Divider Register (REFDV)
PLLCLK 2xOSCCLKx SYNR 1+()
REFDV 1+()
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