Freescale Semiconductor MC9S12XDP512 13.2 External Signal Description, 13.3 Memory Map and Register Denition

Chapter 13 Inter-Integrated Circuit (MC9S12XDP512) Block Description
MC9S12XDP512 Data Sheet, Rev. 2.11
Freescale Semiconductor 595
13.2 External Signal Description
The MC9S12XDP512 module has two external pins.
13.2.1 IIC_SCL — Serial Clock Line Pin
This is the bidirectional serial clock line (SCL) of the module, compatible to the IIC bus specification.
13.2.2 IIC_SDA — Serial Data Line Pin
This is the bidirectional serial data line (SDA) of the module, compatible to the IIC bus specification.
13.3 Memory Map and Register Definition
This section provides a detailed description of all memory and registers for the IIC module.
13.3.1 Module Memory Map
The memory map for the IIC module is given below in Table 13-1. The address listed for each register is
the address offset.The total address for each register is the sum of the base address for the IIC module and
the address offset for each register.
Table 13-1. IIC Memory Map
Address
Offset Use Access
0x0000 IIC-Bus Address Register (IBAD) R/W
0x0001 IIC-Bus Frequency Divider Register (IBFD) R/W
0x0002 IIC-Bus Control Register (IBCR) R/W
0x0003 IIC-Bus Status Register (IBSR) R/W
0x0004 IIC-Bus Data I/O Register (IBDR) R/W