Freescale Semiconductor MC9S12XDP512 11.3.2.16 Pulse Accumulator A Flag Register (PAFLG)

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)
MC9S12XDP512 Data Sheet, Rev. 2.11
532 Freescale Semiconductor
.
11.3.2.16 Pulse Accumulator A Flag Register (PAFLG)
Read: Anytime
Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not
affect the current status of the bit.
NOTE
When TFFCA = 1, the flags cannot be cleared via the normal flag clearing
mechanism (writing a one to the flag). Reference Section 11.3.2.6, “Timer
System Control Register 1 (TSCR1)”.
All bits reset to zero.
0
PAI
Pulse Accumulator Input Interrupt Enable
0 Interrupt inhibited
1 Interrupt requested if PAIF is set
Table 11-19. Pin Action
PAMOD PEDGE Pin Action
0 0 Falling edge
0 1 Rising edge
1 0 Divide by 64 clock enabled with pin high level
1 1 Divide by 64 clock enabled with pin low level
Table 11-20. Clock Selection
CLK1 CLK0 Clock Source
0 0 Use timer prescaler clock as timer counter clock
0 1 Use PACLK as input to timer counter clock
1 0 Use PACLK/256 as timer counter clock frequency
1 1 Use PACLK/65536 as timer counter clock frequency
Module Base + 0x0021
76543210
R000000
PAOVF PAIF
W
Reset 00000000
= Unimplemented or Reserved
Figure 11-36. Pulse Accumulator A Flag Register (PAFLG)
Table 11-18. PACTL Field Descriptions (continued)
Field Description