Freescale Semiconductor MC9S12XDP512 A.5.3 Phase Locked Loop

Appendix A Electrical Characteristics
MC9S12XDP512 Data Sheet, Rev. 2.11
Freescale Semiconductor 947
A.5.3 Phase Locked Loop
The oscillator provides the reference clock for the PLL. The PLL´s voltage controlled oscillator (VCO) is
also the system clock source in self clock mode.
A.5.3.1 XFC Component Selection
This section describes the selection of the XFC components to achieve a good filter characteristics.
Figure A-3. Basic PLL Functional Diagram
The following procedure can be used to calculate the resistance and capacitance values using typical values
for K1, f1 and ich from Table A-22.
The grey boxes show the calculation for fVCO = 80 MHz and fref = 4 MHz. For example, these frequencies
are used for fOSC = 4-MHz and a 40-MHz bus clock.
The VCO gain at the desired VCO frequency is approximated by:
The phase detector relationship is given by:
ich is the current in tracking mode.
The loop bandwidth fCshould be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,
typical values are 50. ζ = 0.9 ensures a good transient response.
fosc fref
Phase
Detector
VCO
KV
1
synr+1
fvco
Loop Divider
KF
1
2
D
fcmp
CsR
Cp
VDDPLL
XFC Pin
1
refdv+1
KVK1e
f1fvco –()
K11V⋅
----------------------------
⋅=195MHz V⁄–e
126 80–
195–
--------------------
⋅== -154.0MHz/V
KΦich –KV ⋅3.5µA–154MHz–V⁄()⋅539.1Hz Ω⁄== =