Chapter 9 XGATE (S12XGATEV2)
MC9S12XDP512 Data Sheet, Rev. 2.11
Freescale Semiconductor 453
Operation
n = RS or IMM4
Shifts the bits in register RD npositions to the left. The lower nbits of the register RD become filled with
zeros. The carry flag will be updated to the bit contained in RD[16-n] before the shift for n > 0.
n can range from 0 to 16.
In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is
equal to 0.
In dyadic address mode, nis determined by the content of RS. nis considered to be 16 if the content of RS
is greater than 15.
CCR Effects
Code and CPU Cycles
LSL Logical Shift Left LSL
NZVC
∆∆∆∆
N: Set if bit 15 of the result is set; cleared otherwise.
Z: Set if the result is $0000; cleared otherwise.
V: Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RD[15]old ^ RD[15]new
C: Set if n > 0 and RD[16-n] = 1; if n = 0 unaffected.
Source Form Address
Mode Machine Code Cycles
LSL RD, #IMM4 IMM4 0 0 0 0 1 RD IMM4 1 1 0 0 P
LSL RD, RS DYA 0 0 0 0 1 RD RS 1 0 1 0 0 P
0
RD
000
n bits
C
n