Freescale Semiconductor MC9S12XDP512 - page 530

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)
MC9S12XDP512 Data Sheet, Rev. 2.11
530 Freescale Semiconductor
Read: Anytime
Write anytime for output compare function. Writes to these registers have no meaning or effect during
input capture.
All bits reset to zero.
Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value of the
free-running counter when a defined transition is sensed by the corresponding input capture edge detector
or to trigger an output action for output compare.
Module Base + 0x001C
15 14 13 12 11 10 9 8
RBit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
W
Reset 00000000
Figure 11-31. Timer Input Capture/Output Compare Register 6 High (TC6)
Module Base + 0x001D
76543210
RBit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
Reset 00000000
Figure 11-32. Timer Input Capture/Output Compare Register 6 Low (TC6)
Module Base + 0x001E
15 14 13 12 11 10 9 8
RBit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
W
Reset 00000000
Figure 11-33. Timer Input Capture/Output Compare Register 7 High (TC7)
Module Base + 0x001F
76543210
RBit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
Reset 00000000
Figure 11-34. Timer Input Capture/Output Compare Register 7 Low (TC7)