Freescale Semiconductor MC9S12XDP512 14.3.2.3 MSCAN Bus Timing Register 0 (CANBTR0)

Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)
MC9S12XDP512 Data Sheet, Rev. 2.11
626 Freescale Semiconductor
14.3.2.3 MSCAN Bus Timing Register 0 (CANBTR0)
The CANBTR0 register configures various CAN bus timing parameters of the MSCAN module.
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Module Base + 0x0002
76543210
R
SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
W
Reset: 00000000
Figure 14-5. MSCAN Bus Timing Register 0 (CANBTR0)
Table 14-4. CANBTR0Register Field Descriptions
Field Description
7:6
SJW[1:0]
Synchronization Jump Width — The synchronization jump width defines the maximum number of time quanta
(Tq) clock cycles a bit can be shortened or lengthened to achieve resynchronization to data transitions on the
CAN bus (see Table 14-5).
5:0
BRP[5:0]
Baud Rate Prescaler — These bits determine the time quanta (Tq) clock which is used to build up the bit timing
(see Table 14-6).
Table 14-5. Synchronization Jump Width
SJW1 SJW0 Synchronization Jump Width
0 0 1 Tq clock cycle
0 1 2 Tq clock cycles
1 0 3 Tq clock cycles
1 1 4 Tq clock cycles
Table 14-6. Baud Rate Prescaler
BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Prescaler value (P)
000000 1
000001 2
000010 3
000011 4
:::::: :
111111 64