Freescale Semiconductor MC9S12XDP512 4.3.2.14 IRQ Control Register (IRQCR)

Chapter 4 Port Integration Module (S12XDP512PIMV2)
MC9S12XDP512 Data Sheet, Rev. 2.11
Freescale Semiconductor 209
4.3.2.14 IRQ Control Register (IRQCR)
Read: See individual bit descriptions below.
Write: See individual bit descriptions below.
6
NCLKX2
No ECLKX2 — This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a fixed
rate of twice the internal bus clock. Clock output is always active in emulation modes and if enabled in all other
operating modes.
0 ECLKX2 is enabled
1 ECLKX2 is disabled
1–0
EDIV[1:0]
Free-Running ECLK Divider — These bits determine the rate of the free-running clock on the ECLK pin. The
usage of the bits is shown in Table 4-17. Divider is always disabled in emulation modes and active as
programmed in all other operating modes.
Table 4-17. Free-Running ECLK Clock Rate
EDIV[1:0] Rate of Free-Running ECLK
00 ECLK = Bus clock rate
01 ECLK = Bus clock rate divided by 2
10 ECLK = Bus clock rate divided by 3
11 ECLK = Bus clock rate divided by 4
0x001E
76543210
R
IRQE IRQEN
000000
W
Reset 01000000
= Unimplemented or Reserved
Figure 4-16. IRQ Control Register (IRQCR)
Table 4-16. ECLKCTL Field Descriptions (continued)
Field Description