Freescale Semiconductor MC9S12XDP512 1.7 COP Conguration, 1.8 ATD0 External Trigger Input Connection

Chapter 1 Device Overview (MC9S12XDP512V2)
MC9S12XDP512 Data Sheet, Rev. 2.11
Freescale Semiconductor 99
1.7 COP Configuration
The COP timeout rate bits CR[2:0] and the WCOP bit in the COPCTL register are loaded on rising edge
of RESET from the Flash control register FCTL ($0107) located in the Flash EEPROM block. See
Table 1-9 and Table 1-10 for coding. The FCTL register is loaded from the Flash configuration field byte
at global address $7FFF0E during the reset sequence
NOTE
If the MCU is secured the COP timeout rate is always set to the longest
period (CR[2:0] = 111) after COP reset.
1.8 ATD0 External Trigger Input Connection
The ATD_10B8C module includes four external trigger inputs ETRIG0, ETRIG1, ETRIG, and ETRIG3.
The external trigger allows the user to synchronize ATD conversion to external trigger events. Table 1-11
shows the connection of the external trigger inputs on MC9S12XDP512.
Table 1-9. Initial COP Rate Configuration
NV[2:0] in
FCTL Register
CR[2:0] in
COPCTL Register
000 111
001 110
010 101
011 100
100 011
101 010
110 001
111 000
Table 1-10. Initial WCOP Configuration
NV[3] in
FCTL Register
WCOP in
COPCTL Register
10
01
Table 1-11. ATD0 External Trigger Sources
External Trigger
Input Connectivity
ETRIG0 Pulse width modulator channel 1
ETRIG1 Pulse width modulator channel 3
ETRIG2 Periodic interrupt timer hardware trigger 0
ETRIG3 Periodic interrupt timer hardware trigger 1