Chapter 1 Device Overview (MC9S12XDP512V2)
MC9S12XDP512 Data Sheet, Rev. 2.11
Freescale Semiconductor 91
1.3 System Clock Description
The clock and reset generator module (CRG) provides the internal clock signals for the core and all
peripheral modules. Figure 1-12 shows the clock connections from the CRG to all modules.
Consult the CRG Block User Guide for details on clock generation.
Figure 1-12. Clock Connections
The MCU’s system clock can be supplied in several ways enabling a range of system operating frequencies
to be supported:
• The on-chip phase locked loop (PLL)
• the PLL self clocking
• the oscillator
The clock generated by the PLL or oscillator provides the main system clock frequencies core clock and
bus clock. As shown in Figure 1-12, this system clocks are used throughout the MCU to drive the core, the
memories, and the peripherals.
SCI0 . . SCI 5
SPI0 . . SPI2
IIC0 & IIC1 ATD0 & ATD1
CAN0 . . CAN4
CRG
Bus Clock
EXTAL
XTAL
Core Clock
Oscillator Clock
RAM S12X XGATE EEPROMFLASH
PIT
ECT
PIM