Freescale Semiconductor MC9S12XDP512 Table 14-2. CANCTL0 Register Field Descriptions (continued)

Chapter 14 Freescale’s Scalable Controller Area Network (S12MSCANV3)
MC9S12XDP512 Data Sheet, Rev. 2.11
Freescale Semiconductor 623
3
TIME
Timer Enable — This bit activates an internal 16-bit wide free running timer which is clocked by the bit clock rate.
If the timer is enabled, a 16-bit time stamp will be assigned to each transmitted/received message within the
active TX/RX buffer. As soon as a message is acknowledged on the CAN bus, the time stamp will be written to
the highest bytes (0x000E, 0x000F) in the appropriate buffer (see Section 14.3.3, “Programmer’s Model of
Message Storage”). The internal timer is reset (all bits set to 0) when disabled. This bit is held low in initialization
mode.
0 Disable internal MSCAN timer
1 Enable internal MSCAN timer
2
WUPE4Wake-Up Enable — This configuration bit allows the MSCAN to restart from sleep mode when traffic on CAN is
detected (see Section 14.4.6.4, “MSCAN Sleep Mode”).
0 Wake-up disabled — The MSCAN ignores traffic on CAN
1 Wake-up enabled — The MSCAN is able to restart
1
SLPRQ5Sleep Mode Request — This bit requests the MSCAN to enter sleep mode, which is an internal power saving
mode (see Section 14.4.6.4, “MSCAN Sleep Mode”). The sleep mode request is serviced when the CAN bus is
idle, i.e., the module is not receiving a message and all transmit buffers are empty. The module indicates entry
to sleep mode by setting SLPAK = 1 (see Section 14.3.2.2, “MSCAN Control Register 1 (CANCTL1)”). Sleep
mode will be active until SLPRQ is cleared by the CPU or, depending on the setting of WUPE, the MSCAN
detects activity on the CAN bus and clears SLPRQ itself.
0 Running — The MSCAN functions normally
1 Sleep mode request — The MSCAN enters sleep mode when CAN bus idle
0
INITRQ6,7 Initialization Mode Request — When this bit is set by the CPU, the MSCAN skips to initialization mode (see
Section 14.4.6.5, “MSCAN Initialization Mode”). Any ongoing transmission or reception is aborted and
synchronization to the CAN bus is lost. The module indicates entry to initialization mode by setting INITAK = 1
(Section 14.3.2.2, “MSCAN Control Register 1 (CANCTL1)”).
The following registers enter their hard reset state and restore their default values: CANCTL08, CANRFLG9,
CANRIER10, CANTFLG, CANTIER, CANTARQ, CANTAAK, and CANTBSEL.
The registers CANCTL1, CANBTR0, CANBTR1, CANIDAC, CANIDAR0-7, and CANIDMR0-7 can only be
written by the CPU when the MSCAN is in initialization mode (INITRQ = 1 and INITAK = 1). The values of the
error counters are not affected by initialization mode.
When this bit is cleared by the CPU, the MSCAN restarts and then tries to synchronize to the CAN bus. If the
MSCAN is not in bus-off state, it synchronizes after 11 consecutive recessive bits on the CAN bus; if the MSCAN
is in bus-off state, it continues to wait for 128 occurrences of 11 consecutive recessive bits.
Writing to other bits in CANCTL0, CANRFLG, CANRIER, CANTFLG, or CANTIER must be done only after
initialization mode is exited, which is INITRQ = 0 and INITAK = 0.
0 Normal operation
1 MSCAN in initialization mode
1The MSCAN must be in normal mode for this bit to become set.
2See the Bosch CAN 2.0A/B specification for a detailed definition of transmitter and receiver states.
3In order to protect from accidentally violating the CAN protocol, the TXCAN pin is immediately forced to a recessive state when
the CPU enters wait (CSWAI = 1) or stop mode (see Section 14.4.6.2, “Operation in Wait Mode” and Section 14.4.6.3,
“Operation in Stop Mode”).
4The CPU has to make sure that the WUPE register and the WUPIE wake-up interrupt enable register (see Section 14.3.2.6,
“MSCAN Receiver Interrupt Enable Register (CANRIER)) is enabled, if the recovery mechanism from stop or wait is required.
5The CPU cannot clear SLPRQ before the MSCAN has entered sleep mode (SLPRQ = 1 and SLPAK = 1).
6The CPU cannot clear INITRQ before the MSCAN has entered initialization mode (INITRQ = 1 and INITAK = 1).
7In order to protect from accidentally violating the CAN protocol, the TXCAN pin is immediately forced to a recessive state when
the initialization mode is requested by the CPU. Thus, the recommended procedure is to bring the MSCAN into sleep mode
(SLPRQ = 1 and SLPAK = 1) before requesting initialization mode.
8Not including WUPE, INITRQ, and SLPRQ.
9TSTAT1 and TSTAT0 are not affected by initialization mode.
10 RSTAT1 and RSTAT0 are not affected by initialization mode.
Table 14-2. CANCTL0 Register Field Descriptions (continued)
Field Description