512 Kbyte Flash Module (S12XFTX512K4V2)
BookTitle, Rev. 2.4
Freescale Semiconductor 137
Figure 2-30. Example Mass Erase Command Flow
Write: Flash Block Address
Write: FCMD register
Mass Erase Command 0x41
Write: FSTAT register
Clear CBEIF 0x80
1.
2.
3.
Clear ACCERR/PVIOL 0x30
Write: FSTAT register
yes
no
Access Error and
Protection Violation
and Dummy Data
Read: FSTAT register
Read: FSTAT register
no
START
yes
Check
CBEIF
Set?
Next
no
yes
Address, Data,
Command
Buffer Empty Check
Flash
Block?
ACCERR/
PVIOL
Set?
EXIT
by 128K
Decrement Global Address
Write: FCLKDIV register
Read: FCLKDIV register
yes
no
Clock Register
Written
Check
FDIVLD
Set?
NOTE: FCLKDIV needs to
be set once after each reset.
Simultaneous
Multiple Flash Block
Decision
no
Bit Polling for
Command Completion
Check
yes
CCIF
Set?