Freescale Semiconductor MC9S12XDP512 11.3.2.14 Timer Input Capture/Output Compare Registers 07

Chapter 11 Enhanced Capture Timer (S12MC9S12XDP51216B8CV2)
MC9S12XDP512 Data Sheet, Rev. 2.11
528 Freescale Semiconductor
11.3.2.14 Timer Input Capture/Output Compare Registers 0–7
Module Base + 0x0010
15 14 13 12 11 10 9 8
RBit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
W
Reset 00000000
Figure 11-19. Timer Input Capture/Output Compare Register 0 High (TC0)
Module Base + 0x0011
76543210
RBit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
Reset 00000000
Figure 11-20. Timer Input Capture/Output Compare Register 0 Low (TC0)
Module Base + 0x0012
15 14 13 12 11 10 9 8
RBit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
W
Reset 00000000
Figure 11-21. Timer Input Capture/Output Compare Register 1 High (TC1)
Module Base + 0x0013
76543210
RBit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
Reset 00000000
Figure 11-22. Timer Input Capture/Output Compare Register 1 Low (TC1)
Module Base + 0x0014
15 14 13 12 11 10 9 8
RBit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
W
Reset 00000000
Figure 11-23. Timer Input Capture/Output Compare Register 2 High (TC2)
Module Base + 0x0015
76543210
RBit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
Reset 00000000
Figure 11-24. Timer Input Capture/Output Compare Register 2 Low (TC2)