Chapter 23 Memory Mapping Control (S12XMMCV2)
MC9S12XDP512 Data Sheet, Rev. 2.11
886 Freescale Semiconductor
The MMCCTL0 register is used to control external bus functions, i.e., availability of chip selects.
CAUTION
XGATE write access to this register during an CPU access which makes useof this register could lead to unexpected results.

Table 23-4. MMCCTL0 Field Descriptions

Field Description
3–0
CS[3:0]E
Chip Select Enables — Each of these bits enables one of the external chip selects CS3, CS2, CS1, and CS0
outputs which are asserted during accesses to specific external addresses. The associated global address
ranges are shown in Table 1-6 and Table 1-21 and Figure 1-23.
Chip selects are only active if enabled in normal expanded mode, Emulation expanded mode and special test
mode. The function disabled in all other operating modes.
0 Chip select is disabled
1 Chip select is enabled

Table 23-5. Chip Select Signals

Global Address Range Asserted Signal
0x00_0800–0x0F_FFFF CS3
0x10_0000–0x1F_FFFF CS2
0x20_0000–0x3F_FFFF CS1
0x40_0000–0x7F_FFFF CS01
1When the internal NVM is enabled (see ROMON in Section 1.3.2.5, “MMC Control
Register (MMCCTL1)”) the CS0 is not asserted in the space occupied by this on-chip
memory block.